LTC1448
Dual 12-Bit Rail-to-Rail
Micropower DAC
FEATURES
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DESCRIPTION
The LTC
®
1448 is a dual rail-to-rail voltage output, 12-bit
digital-to-analog converter (DAC). It includes rail-to-rail
output buffer amplifiers and an easy-to-use 3-wire serial
interface. It is available in 8-pin SO and PDIP packages and
provides the smallest footprint of any dual 12-bit DAC.
The LTC1448 has an external reference input pin (REF)
and its outputs swing from 0V to REF. The REF input can
be tied to V
CC
providing rail-to-rail operation from supplies
of 2.7V to 5.5V. (For devices with internal reference see the
LTC1446 data sheet.) The LTC1448 dissipates 2.5mW
from a 5V supply.
The low power supply current and the small SO-8 package
make the LTC1448 ideal for battery-powered applications.
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SO-8 Package
12-Bit Resolution
Buffered True Rail-to-Rail Voltage Output
External Reference Input Can Be Tied to V
CC
Output Swings from 0V to V
REF
3V and 5V Supply Operation
Schmitt Trigger on Clock Input Allows Direct
Optocoupler Interface
Power-On Reset Clears DACs to 0V
3-Wire Serial Interface
Maximum DNL Error: 0.5LSB
Low Cost
APPLICATIONS
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Digital Calibration
Industrial Process Control
Automatic Test Equipment
Cellular Telephones
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
Functional Block Diagram: 12-Bit Rail-to-Rail Dual DAC
2.7V TO 5.5V
0.5
7
V
CC
2 D
IN
4
REF
DNL ERROR (LSB)
+
12-BIT
DAC B
V
OUT B
8
µP
1 CLK
3 CS/LD
24-BIT
SHIFT
REG
AND
DAC
LATCH
–
RAIL-TO-RAIL
VOLTAGE
OUTPUTS
+
12-BIT
DAC A
V
OUT A
5
–
POWER-ON
RESET
GND
6
1448 TA01
U
U
U
Differential Nonlinearity
vs Input Code
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
1448 TA02
1
LTC1448
ABSOLUTE
MAXIMUM
RATINGS
V
CC
to GND .............................................. – 0.5V to 7.5V
Logic Inputs to GND ................................ – 0.5V to 7.5V
V
OUT A
, V
OUT B
, REF to GND ........... – 0.5V to V
CC
+ 0.5V
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC1448C ............................................ 0°C to 70°C
LTC1448I......................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
PACKAGE/ORDER I FOR ATIO
TOP VIEW
CLK 1
D
IN
2
CS/LD 3
REF 4
N8 PACKAGE
8-LEAD PDIP
8
7
6
5
V
OUT B
V
CC
GND
V
OUT A
ORDER PART
NUMBER
LTC1448CN8
LTC1448IN8
LTC1448CS8
LTC1448IS8
S8 PART MARKING
1448
1448I
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 125°C,
θ
JA
= 100°C/W (N8)
T
JMAX
= 125°C,
θ
JA
= 150°C/W (S8)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
V
CC
= 2.7V to 5.5V, V
OUT A
and V
OUT B
unloaded, REF
≤
V
CC
, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
SYMBOL
DAC
Resolution
Monotonicity
DNL
INL
V
OS
V
OS
TC
V
FS
V
FS
TC
Differential Nonlinearity
Integral Nonlinearity
Offset Error
Offset Error Temperature
Coefficient
Full-Scale Voltage
Full-Scale Voltage
Temperature Coefficient
Positive Supply Voltage
Supply Current
Short-Circuit Current Low
Short-Circuit Current High
Output Impedance to GND
Output Line Regulation
For Specified Performance
(Note 4)
V
OUT
Shorted to GND
V
OUT
Shorted to V
CC
Input Code = 0
Input Code = 4095. V
CC
= 4.5V to 5.5V, V
REF
= 4.096V
q
q
q
q
PARAMETER
CONDITIONS
MIN
12
12
TYP
MAX
UNITS
Bits
Bits
V
REF
≤
V
CC
– 0.1V (Note 1)
V
REF
≤
V
CC
– 0.1V (Note 1), T
A
= 25°C
V
REF
≤
V
CC
– 0.1V (Note 1)
Measured at Code 20, T
A
= 25°C
Measured at Code 20
q
q
q
± 0.2
± 0.5
± 5.0
± 5.5
± 10
± 15
±15
V
REF
= 4.096V, T
A
= 25°C
V
REF
= 4.096V
4.070
4.060
4.095
4.095
10
4.120
4.130
µV/°C
V
V
ppm/°C
q
Power Supply
V
CC
I
CC
2.7
450
55
65
30
0.2
5.5
700
120
120
120
1.5
V
µA
mA
mA
Ω
LSB/V
Op Amp DC Performance
q
q
q
q
2
U
LSB
LSB
LSB
mV
mV
W
U
U
W W
W
LTC1448
ELECTRICAL CHARACTERISTICS
V
CC
= 2.7V to 5.5V, V
OUT A
and V
OUT B
unloaded, REF
≤
V
CC
, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
SYMBOL
PARAMETER
Voltage Output Slew Rate
Voltage Output Settling Time
Digital Feedthrough
Reference Input
R
IN
REF
Digital I/O
V
IH
V
IL
I
LEAK
C
IN
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Leakage
Digital Input Capacitance
D
IN
Valid to CLK Setup
D
IN
Valid to CLK Hold
CLK High Time
CLK Low Time
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
CLK Low to CS/LD Low
D
IN
Valid to CLK Setup
D
IN
Valid to CLK Hold
CLK High Time
CLK Low Time
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
CLK Low to CS/LD Low
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
V
CC
= 5V
V
CC
= 3V
V
CC
= 5V
V
CC
= 3V
V
IN
= GND to V
CC
(Note 6)
q
q
q
q
q
q
CONDITIONS
q
MIN
0.5
TYP
1.0
14
0.3
MAX
UNITS
V/µs
µs
nV • s
AC Performance
(Notes 2, 3) to ± 0.5LSB
REF Input Resistance
REF Input Range
(Notes 5, 6)
q
q
7.5
0
2.4
2.0
12.5
18
V
CC
kΩ
V
V
V
0.8
0.6
± 10
10
40
0
40
40
50
40
20
20
60
0
60
60
80
60
30
30
V
V
µA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching (V
CC
= 4.5V to 5.5V)
q
q
q
q
q
q
q
q
Switching (V
CC
= 2.7V to 5.5V)
q
q
q
q
q
q
q
q
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
Nonlinearity is defined from code 20 to code 4095 (full scale).
See Applications Information.
Note 2:
Load is 5k in parallel with 100pF.
Note 3:
DAC switched between all 1s and the code corresponding to V
OS
for the part.
Note 4:
Digital inputs at 0V or V
CC
.
Note 5:
V
OUT
can only swing from (GND +
V
OS
)
to (V
CC
–
V
OS
)
when
output is unloaded.
Note 6.
Guaranteed by design, not subject to test.
3
LTC1448
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
5
4
3
INL ERROR (LSB)
DNL ERROR (LSB)
2
1
0
–1
–2
–3
–4
–5
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
1448 G01
V
CC
– V
OUT
(V)
Minimum Output Voltage vs
Output Sink Current
800
OUTPUT PULL-DOWN VOLTAGE (mV)
CODE: ALL 0’s
700
SUPPLY CURRENT (mA)
600
125°C
500
400
300
–55°C
200
100
0
25°C
0
5
10
OUTPUT SINK CURRENT (mA)
PIN FUNCTIONS
CLK (Pin 1):
Serial Interface Clock. Internal Schmitt trig-
ger on this input allows direct optocoupler interface.
D
IN
(Pin 2):
Serial Interface Data. Data on the D
IN
pin is
latched into the shift register on the rising edge of the serial
clock.
CS/LD (Pin 3):
Serial Interface Enable and Load Control.
When CS/LD is low the CLK signal is enabled, so the data
can be clocked in. When CS/LD is pulled high, data is
loaded from the shift register into the DAC register,
updating the DAC output and the CLK is disabled
internally.
REF (Pin 4):
Reference Input for Both DACs. This pin can
be tied to V
CC
. The output will swing from 0V to REF. The
typical input resistance is 12.5k.
V
OUT A
, V
OUT B
(Pins 5, 8):
Buffered DAC Outputs.
GND (Pin 6):
Ground.
V
CC
(Pin 7):
Positive Supply Input. 2.7V
≤
V
CC
≤
5.5V.
Requires a bypass capacitor to ground.
4
U W
Differential Nonlinearity (DNL)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
1448 TA02
Minimum Supply Headroom for
Full Output Swing vs Load Current
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
5
10
LOAD CURRENT (mA)
15
1448 G03
∆V
OUT
< 1LSB
CODE: ALL 1’s
V
OUT
= 4.095V
Supply Current vs
Logic Input Voltage
2.0
1.6
1.2
0.8
0.4
0
15
1448 G04
0
1
3
4
2
LOGIC INPUT VOLTAGE (V)
5
1448 G06
U
U
U
LTC1448
BLOCK DIAGRA
W
LD
CLK 1
DAC B
REGISTER
12-BIT
DAC B
+
8
V
OUT B
–
D
IN
2
24-BIT
SHIFT
REGISTER
LD
CS/LD 3
REF 4
DAC A
REGISTER
12-BIT
DAC A
7
V
CC
6
GND
+
5
V
OUT A
–
POWER-ON
RESET
1448 BD
TI I G DIAGRA S
OPERATING SEQUENCE
DAC A INPUT
MSB
D
IN
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB MSB
D0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DAC B INPUT
LSB
D0
CLK
1
2
3
4
CS/LD
(ENABLE CLOCK)
(UPDATE DAC OUTPUT)
1448 TD01
CLK
t
8
B0-B
PREVIOUS WORD
B11-A
MSB
B0-A
LSB
B11-B
MSB
B0-B
LSB
t
5
CS/LD
1448 TD02
D
IN
W
5
UW
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
t
4
t
3
t
1
t
2
t
6
t
7
5
嵌入式系统
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