LTC1454/LTC1454L
Dual 12-Bit Rail-to-Rail
Micropower DACs
FEATURES
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DESCRIPTION
The LTC
®
1454/LTC1454L are complete single supply,
dual rail-to-rail voltage output, 12-bit digital-to-analog
converters (DACs) in a 16-lead SO package. They include
an output buffer amplifier with variable gain (×1 or
×
2)
and an easy-to-use 3-wire cascadable serial interface.
The LTC1454 has an onboard reference of 2.048V and a
full-scale output of 4.095V in a
×
2 gain configuration. It
operates from a single 4.5V to 5.5V supply.
The LTC1454L has an onboard 1.22V reference and a full-
scale output of 2.5V in a
×
2 gain configuration. It operates
from a single 2.7V to 5.5V supply.
Low power supply current, excellent DNL and small size
allow these parts to be used in a host of applications where
size, DNL and single supply operation are important.
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12-Bit Resolution
Buffered True Rail-to-Rail Voltage Output
5V Operation, I
CC
: 700µA Typ (LTC1454)
3V Operation, I
CC
: 450µA Typ (LTC1454L)
Built-In Reference: 2.048V (LTC1454)
1.220V (LTC1454L)
CLR Pin
Power-On Reset
16-Lead SO Package
3-Wire Cascadable Serial Interface
Maximum DNL Error: 0.5LSB
Low Cost
APPLICATIONS
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Digital Calibration
Industrial Process Control
Automatic Test Equipment
Cellular Telephones
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
Daisy-Chained
Dual 12-Bit Rail-to-Rail DAC
Functional Block Diagram:
Control Outputs
LTC1454: 5V
LTC1454L: 3V TO 5V
9, 15
V
CC
LTC1454: 2.048V
10 LTC1454L: 1.22V
REFOUT
REFHI B 14
0.5
0.4
0.3
DNL ERROR (LSB)
+
4 D
IN
µP
3 CLK
5 CS/LD
6 D
OUT
12-BIT
DAC B
24-BIT
SHIFT
REG
AND
DAC
LATCH
V
OUT B
16
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
1454 G08
–
X1/X2 B 1
REFHI A
11
+
12-BIT
DAC A
V
OUT A
8
–
X1/X2 A
7
POWER-ON
RESET
CLR
2
12
REFLO
GND
13
1454 BD02
U
U
U
Differential Nonlinearity
vs Input Code
1
LTC1454/LTC1454L
ABSOLUTE
MAXIMUM
RATINGS
V
CC
to GND .............................................. – 0.5V to 7.5V
Logic Inputs to GND ................................ – 0.5V to 7.5V
V
OUT A
, V
OUT B
, X1/X2 A ,
X1/X2 B ..................................... – 0.5V to V
CC
+ 0.5V
REFHI A , REFHI B, REFLO ............. – 0.5V to V
CC
+ 0.5V
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC1454C/LTC1454LC ............................ 0°C to 70°C
LTC1454I/LTC1454LI ........................ – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
PACKAGE/ORDER I FOR ATIO
TOP VIEW
X1/X2 B 1
CLR 2
CLK 3
D
IN
4
CS/LD 5
D
OUT
6
X1/X2 A 7
V
OUT A
8
16 V
OUT B
15 V
CC
14 REFHI B
13 GND
12 REFLO
11 REFHI A
10 REFOUT
9
V
CC
ORDER PART
NUMBER
LTC1454CN
LTC1454IN
LTC1454CS
LTC1454IS
LTC1454LCN
LTC1454LIN
LTC1454LCS
LTC1454LIS
N PACKAGE
S PACKAGE
16-LEAD PDIP 16-LEAD PLASTIC SO
T
JMAX
= 125°C,
θ
JA
= 100°C/W (N)
T
JMAX
= 125°C,
θ
JA
= 150°C/W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
V
CC
= 4.5V to 5.5V (LTC1454), 2.7V to 5.5V (LTC1454L), X1/X2 = REFLO = GND, REFHI = REFOUT, V
OUT
and REFOUT unloaded,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.
SYMBOL
DAC
Resolution
DNL
INL
V
OS
V
OS
TC
V
FS
Differential Nonlinearity
Integral Nonlinearity
Offset Error
Offset Error Temperature
Coefficient
Full-Scale Voltage
When Using Internal Reference, LTC1454, T
A
= 25°C
LTC1454
When Using Internal Reference, LTC1454L, T
A
= 25°C
LTC1454L
V
FS
TC
Reference
Reference Output Voltage
Reference Output
Temperature Coefficient
Reference Line Regulation
Reference Load Regulation
Reference Input Range
Reference Input Resistance
Reference Input Capacitance
Short-Circuit Current
REFOUT Shorted to GND
q
q
q
q
q
PARAMETER
CONDITIONS
MIN
12
TYP
MAX
UNITS
Bits
Guaranteed Monotonic (Note 1)
T
A
= 25°C
(Note 1)
T
A
= 25°C
q
q
q
±
0.5
±2.0
±2.5
±2.0
±4.0
±15
4.065
4.045
2.470
2.460
4.095
4.095
2.500
2.500
±
24
4.125
4.145
2.530
2.540
±4.0
±4.5
±12
±18
µV/°C
V
V
V
V
ppm/°C
Full-Scale Voltage
Temperature Coefficient
When Using Internal Reference
LTC1454
LTC1454L
q
q
2.008
1.195
2.048
1.220
±20
0.7
0.2
0.6
V
CC
/ 2
2.088
1.245
ppm/°C
±2.0
1.5
3.0
40
120
LSB/V
LSB
LSB
V
kΩ
pF
mA
0
≤
I
OUT
≤
100µA, LTC1454
LTC1454L
V
REFHI
≤
V
CC
– 1.5V
q
q
q
15
24
15
40
2
U
LSB
LSB
LSB
mV
mV
V
V
W
U
U
W W
W
LTC1454/LTC1454L
ELECTRICAL CHARACTERISTICS
V
CC
= 4.5V to 5.5V (LTC1454), 2.7V to 5.5V (LTC1454L), X1/X2 = REFLO = GND, REFHI = REFOUT, V
OUT
and REFOUT unloaded,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.
SYMBOL
V
CC
I
CC
PARAMETER
Positive Supply Voltage
Supply Current
CONDITIONS
For Specified Performance, LTC1454
LTC1454L
4.5V
≤
V
CC
≤
5.5V (Note 4), LTC1454
2.7V
≤
V
CC
≤
5.5V (Note 4), LTC1454L
V
OUT
Shorted to GND
V
OUT
Shorted to V
CC
Input Code = 0
(Note 2)
(Notes 2, 3) to
±0.5LSB
REFHI = 1kHz, 2V
P-P
, (Code: All 0s)
REFHI = 1kHz, 2V
P-P
, (Code: All 1s)
q
q
q
q
MIN
4.5
2.7
TYP
MAX
5.5
5.5
UNITS
V
V
µA
µA
mA
mA
Ω
V/µs
µs
nV • s
dB
dB
Power Supply
700
450
70
80
40
0.5
1.0
14
0.3
– 95
85
1250
1100
120
120
Op Amp DC Performance
Short-Circuit Current Low
Short-Circuit Current High
Output Impedance to GND
AC Performance
Voltage Output Slew Rate
Voltage Output Settling Time
Digital Feedthrough
AC Feedthrough
SINAD
Signal-to-Noise + Distortion
q
q
q
q
V
CC
= 5V (LTC1454), 3V (LTC1454L), T
A
= T
MIN
to T
MAX
, unless otherwise noted.
SYMBOL
Digital I/O
V
IH
V
IL
V
OH
V
OL
I
LEAK
C
IN
Switching
t
1
t
2
t
3
t
4
t
5
t
6
t7
t
8
t
9
D
IN
Valid to CLK Setup
D
IN
Valid to CLK Hold
CLK High Time
CLK Low Time
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
D
OUT
Output Delay
CLK Low to CS/LD Low
C
LOAD
= 15pF
q
q
q
q
q
q
q
q
q
PARAMETER
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage
Digital Input Capacitance
CONDITIONS
q
q
LTC1454
MIN
TYP
MAX
2.4
0.8
V
CC
– 1.0
0.4
±10
10
40
0
40
40
50
40
20
150
20
LTC1454L
MIN
TYP
MAX
2.0
0.6
V
CC
– 0.7
0.4
±10
10
60
0
60
60
80
60
30
220
30
UNITS
V
V
V
V
µA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
OUT
= – 1mA
I
OUT
= 1mA
V
IN
= GND to V
CC
Guaranteed by Design
q
q
q
q
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to code 4095 (full scale).
Note 2:
Load is 5kΩ in parallel with 100pF.
Note 3:
DAC switched between all 1s and the code corresponding to V
OS
for the part.
Note 4:
Digital inputs at 0V or V
CC
.
3
LTC1454/LTC1454L
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1454
Differential Nonlinearity
0.5
0.4
0.3
2.0
1.6
1.2
INL ERROR (LSB)
DNL ERROR (LSB)
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
1454 G08
V
CC
– V
OUT
(V)
LTC1454 Minimum Output
Voltage vs Output Sink Current
1000
OUTPUT PULL-DOWN VOLTAGE (mV)
900
800
700
600
500
400
300
200
100
0.1
0
REFLO = GND
X1/X2 = GND
125°C
25°C
OUTPUT SWING (V)
OUTPUT SWING (V)
5
10
15
20
25
OUTPUT SINK CURRENT (mA)
LTC1454 Full-Scale Voltage vs
Temperature
4.110
4.105
SFULL-SCALE VOLTAGE (V)
SUPPLY CURRENT (µA)
740
730
720
710
700
690
–55
V
CC
= 5.5V
4.100
4.095
4.090
4.085
4.080
–55
SUPPLY CURRENT (mA)
–25
5
35
65
TEMPERATURE (°C)
4
U W
–55°C
1454 G04
LTC1454
Integral Nonlinearity
1.0
Minimum Supply Headroom for
Full Output Swing vs Load Current
∆V
OUT
< 1LSB
REFLO = GND
X1/X2 = GND
CODE: ALL 1's
V
OUT
= 4.095V
0.8
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
–2.0
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
1454 G07
0.6
0.4
0.2
0
0
5
10
15
20
LOAD CURRENT (mA)
25
30
1454 G03
LTC1454 Output Swing vs
Load Resistance
4.5
4.0
3.5
3.0
2.5
2.0
R
L
LTC1454 Output Swing vs
Load Resistance
4.5
4.0
3.5
3.0
V
CC
REFLO = GND
X1/X2 = GND
REFLO = GND
X1/X2 = GND
2.5
2.0
1.5
1.0
0.5
0
R
L
1.5
1.0
0.5
30
0
10
100
1k
LOAD RESISTANCE (Ω)
10k
1454 G05
10
100
1k
LOAD RESISTANCE (Ω)
10k
1458 G06
LTC1454
Supply Current vs Temperature
760
750
2.1
2.6
LTC1454 Supply Current vs
Logic Input Voltage
1.6
V
CC
= 5V
1.1
V
CC
= 4.5V
0.6
95
125
1454 G02
–25
35
65
5
TEMPERATURE (°C)
95
125
1454 G01
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOGIC INPUT VOLTAGE (V)
1454 G09
LTC1454/LTC1454L
PIN FUNCTIONS
X1/X2 B, X1/X2 A (Pins 1, 7):
The Input Pin that Sets the
Gain for DAC A/B. When grounded the gain will be 2, i.e.,
output full scale will be
×
2 REFHI. When connected to
V
OUT
the gain will be 1, i.e., output full scale will be equal
to REFHI.
CLR (Pin 2):
The Clear Pin for the DAC. Clears both DACs
to zero scale when pulled low. This pin should be tied to
V
CC
for normal operation.
CLK (Pin 3):
The Serial Interface Clock Input.
D
IN
(Pin 4):
The Serial Data Input. Data on the D
IN
pin is
latched into the shift register on the rising edge of the serial
clock. Data is loaded as one 24-bit word. The first 12 bits
are for DAC A, MSB-first and the second 12 bits are for
DAC B, MSB-first.
CS/LD (Pin 5):
The Serial Interface Enable and Load
Control Input. When CS/LD is low the CLK signal is
enabled so the data can be clocked in. When CS/LD is
pulled high, data is loaded from the shift register into the
DAC register, updating the DAC output.
D
OUT
(Pin 6):
The Output of the Shift Register which
Becomes Valid on the Rising Edge of the Serial Clock.
V
OUT A,
V
OUT B
(Pins 8, 16):
The Buffered DAC Outputs.
V
CC
(Pins 9, 15):
The Positive Supply Input. 4.5
≤
V
CC
≤
5.5V (LTC1454), 2.7V
≤
V
CC
≤
5.5V (LTC1454L). Re-
quires a bypass capacitor to ground.
REFOUT (Pin 10):
The Output of the Internal Reference.
REFHI A , REFHI B (Pins 11,14):
The Inputs to the DAC
Resistor Ladder for DAC A/B.
REFLO (Pin 12):
The Bottom of the DAC Resistor Ladder
for Both DACs. This can be used to offset zero-scale above
ground. REFLO should be connected to ground when no
offset is required.
GND (Pin 13):
Ground.
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U
U
5
stm32/stm8
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