Final Electrical Specifications
LTC1654
Dual 14-Bit Rail-to-Rail DAC
in 16-Lead SSOP Package
FEATURES
s
s
April 2000
DESCRIPTIO
s
s
s
s
s
s
s
14-Bit Monotonic Over Temperature
Individually Programmable Speed/Power:
3.5µs Settling Time at 750µA
8µs Settling Time at 450µA
Maximum Update Rate: 0.9MHz
Smallest Dual 14-Bit DAC: 16-Lead Narrow
SSOP Package
Buffered True Rail-to-Rail Voltage Outputs
3V to 5V Single Supply Operation
User Selectable Gain
Power-On Reset and Clear Function
Schmitt Trigger On Clock Input Allows Direct
Optocoupler Interface
The LTC
®
1654 is a dual, rail-to-rail voltage output, 14-bit
digital-to-analog converter (DAC). It is available in a
16-lead narrow SSOP package, making it the smallest dual
14-bit DAC available. It includes output buffer amplifiers
and a flexible serial interface.
The LTC1654 has REFHI pins for each DAC that can be
driven up to V
CC
. The output will swing from 0V to V
CC
in
gain of 1 configuration or V
CC
/2 in gain of 1/2 configura-
tion. It operates from a single 2.7V to 5.5V supply.
The LTC1654 has two programmable speeds: a FAST and
SLOW mode with
±1LSB
settling times of 3.5µs or 8µs
respectively and supply currents of 750µA and 450µA in
the two modes. The LTC1654 also has shutdown capabil-
ity, power-on reset and clear function to 0V.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s
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Digital Calibration
Industrial Process Control
Automatic Test Equipment
Offset/Gain Adjustment
BLOCK DIAGRA
CS/LD
SCK
CONTROL
LOGIC
SDI
INPUT
LATCH
DAC
REGISTER
DAC B
+
V
OUT B
–
32-BIT
SHIFT
REGISTER
X
1
/X
1/2
B
REFHI A
INPUT
LATCH
DAC
REGISTER
DAC A
+
V
OUT A
SDO
POWER-ON
RESET
REFLO B
REFLO A
–
X
1
/X
1/2
A
1654 BD
CLR
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
REFHI B
W
U
1
LTC1654
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
X
1
/X
1/2
B
CLR
SCK
SDI
CS/LD
DGND
SDO
X
1
/X
1/2
A
1
2
3
4
5
6
7
8
16 V
CC
15 V
OUT B
14 REFHI B
13 REFLO B
12 AGND
11 REFLO A
10 REFHI A
9
V
OUT A
V
CC
to GND .............................................. – 0.5V to 7.5V
TTL Input Voltage, REFHI,
REFLO, X
1
/X
1/2
........................................ – 0.5V to 7.5V
V
OUT
, SDO .................................. – 0.5V to (V
CC
+ 0.5V)
Operating Temperature Range
LTC1654C ............................................. 0°C to 70°C
LTC1654I ........................................ – 40°C to 85°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
LTC1654CGN
LTC1654IGN
GN PART MARKING
1654
1654I
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
T
JMAX
= 125°C,
θ
JA
= 95°C/ W
Consult factory for Military grade parts.
The
q
denotes specifications which apply over the full operating tempera-
ture range, otherwise specifications are at T
A
= 25°C, V
CC
= 2.7V to 5.5V, V
OUT A
, V
OUT B
unloaded, REFHI A, REFHI B = 4.096V
(V
CC
= 5V), REFHI A, REFHI B = 2.048V (V
CC
= 2.7V), REFLO = 0V, X
1
/X
1/2
= 0V.
SYMBOL
DAC
Resolution
Monotonicity
DNL
INL
ZSE
V
OS
V
OS
TC
Differential Nonlinearity
Integral Nonlinearity
Zero Scale Error
Offset Error
Offset Error Tempco
Gain Error
Gain Error Drift
Power Supply
V
CC
I
CC
Positive Supply Voltage
Supply Current (SLOW/FAST)
For Specified Performance
2.7V
≤
V
CC
≤
5.5V (Note 5) SLOW
2.7V
≤
V
CC
≤
5.5V (Note 5) FAST
2.7V
≤
V
CC
≤
3.3V (Note 5) SLOW
2.7V
≤
V
CC
≤
3.3V (Note 5) FAST
In Shutdown (Note 5)
V
OUT
Shorted to GND
V
OUT
Shorted to V
CC
Input Code = 0
Input Code = 16383, V
CC
= 2.7V to 5.5V,
V
REF
= 2.048V
q
q
q
q
q
q
q
q
q
q
q
q
q
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
14
14
TYP
MAX
UNITS
Bits
Bits
Guaranteed Monotonic (Note 2)
Integral Nonlinearity (Note 2)
C Grade
I Grade
Measured at Code 50, C Grade
Measured at Code 50, I Grade
q
q
q
q
q
q
±1
±4
0
6.5
9.0
±6.5
±9.0
±15
±15
5
2.7
450
750
250
450
7
70
80
40
5.5
800
1300
500
900
30
120
120
200
2.25
ppm/°C
V
µA
µA
µA
µA
µA
mA
mA
Ω
mV/V
Op Amp DC Performance
Short-Circuit Current Low
Short-Circuit Current High
Output Impedance to GND
Output Line Regulation
2
U
LSB
LSB
mV
mV
mV
mV
µV/°C
LSB
W
U
U
W W
W
LTC1654
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
Voltage Output Slew Rate
Voltage Output Settling Time
Digital Feedthrough
Midscale Glitch Impulse
Output Noise Voltage Density
Digital I/O
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
OH
V
OL
I
LEAK
C
IN
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage
Digital Input Capacitance
Reference Input Resistance
Reference Input Range
Reference Input Current
Switching Characteristics (V
CC
= 4.5V to 5.5V)
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
SDI Valid to SCK Setup
SDI Valid to SCK Hold
SCK High Time
SCK Low Time
CS/LD Pulse Width
LSB SCK to CS/LD
CS/LD Low to SCK
SD0 Output Delay
SCK Low to CS/LD Low
SDI Valid to SCK Setup
SDI Valid to SCK Hold
SCK High Time
SCK Low Time
CS/LD Pulse Width
LSB SCK to CS/LD
CS/LD Low to SCK
SDO Output Delay
SCK Low to CS/LD Low
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
V
CC
= 5V
V
CC
= 5V
CONDITIONS
AC Performance
The
q
denotes specifications which apply over the full operating tempera-
ture range, otherwise specifications are at T
A
= 25°C, V
CC
= 2.7V to 5.5V, V
OUT A
, V
OUT B
unloaded, REFHI A, REFHI B = 4.096V
(V
CC
= 5V), REFHI A, REFHI B = 2.048V (V
CC
= 2.7V), REFLO = 0V, X
1
/X
1/2
= 0V.
MIN
q
q
TYP
MAX
UNITS
V/µs
V/µs
(Note 3) SLOW
(Note 3) FAST
(Note 4) to
±1LSB,
SLOW
(Note 4) to
±1LSB,
FAST
(Note 8)
DAC Switch Between 8000 and 7FFF
at 1kHz, SLOW
at 1kHz, FAST
0.20
1.25
8.0
3.5
1
20
540
320
µs
µs
nV•s
nV•s
nV/√Hz
nV/√Hz
V
0.8
V
V
0.4
V
V
0.8
V
V
0.4
±10
10
V
µA
pF
kΩ
V
CC
1
V
µA
ns
ns
ns
ns
ns
ns
ns
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
150
ns
ns
q
q
q
q
q
q
q
q
q
2.4
V
CC
– 0.75
2.4
V
CC
– 0.75
V
CC
= 5V, I
OUT
= – 1mA, D
OUT
Only
V
CC
= 5V, I
OUT
= 1mA, D
OUT
Only
V
CC
= 3V
V
CC
= 3V
V
CC
= 3V, I
OUT
= – 1mA, D
OUT
Only
V
CC
= 3V, I
OUT
= 1mA, D
OUT
Only
V
IN
= GND to V
CC
(Note 6)
REFHI to REFLO
(Notes 6, 7)
In Shutdown
Reference Input
q
q
q
30
0
60
q
q
q
q
q
q
q
q
q
30
0
15
15
15
10
10
5
10
45
0
20
20
20
15
15
5
15
C
LOAD
= 100pF
(Note 6)
Switching Characteristics (V
CC
= 2.7V to 5.5V)
q
q
q
q
q
q
q
q
q
C
LOAD
= 100pF
(Note 6)
3
LTC1654
ELECTRICAL CHARACTERISTICS
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
Nonlinearity is defined from code 50 to code 16383 (full scale).
See Applications Information.
Note 3:
100pF Load Capacitor
Note 4:
DAC switched between code 200 and code 16383.
Note 5:
Digital inputs at 0V or V
CC
.
Note 6:
Guaranteed by design.
Note 7:
V
OUT
can only swing from (GND +V
OS
)
to (V
CC
–V
OS
)
when output is unloaded. See Applications Information.
Note 8:
CS/LD = 0, V
OUT
= 4.096 and data is being clocked in.
PI FU CTIO S
X
1
/X
1/2
B, X
1
/X
1/2
A (Pins 1, 8):
The Gain of 1 or Gain of
1/2 Pin. When this pin is tied to V
OUT
, the output will swing
up to REFHI/2 and when this pin is tied to REFLO, the
output will swing up to REFHI. These pins should not be
left floating.
CLR (Pin 2):
The Asynchronous Clear Input.
SCK (Pin 3):
The TTL Level Input for the Serial Interface
Clock.
SDI (Pin 4):
The TTL Level Input for the Serial Interface
Data. Data on the SDI pin is latched into the shift register
on the rising edge of the serial clock. The LTC1654 re-
quires a 24-bit word. The first 8 bits are control/address
followed by 16 data bits. The last two of the 16 data bits are
don’t cares. If daisy-chaining is desired, then a 32-bit data
word can be used with the first 8 being don’t cares and the
following 24 bits as above.
CS/LD (Pin 5):
The TTL Level Input for the Serial Interface
Enable and Load Control. When CS/LD is low, the SCK
signal is enabled, so the data can be clocked in. When
CS/LD is pulled high, the control/address bits are
decoded.
DGND/AGND (Pins 6, 12):
Digital and Analog Grounds.
SDO (Pin 7):
The output of the shift register that becomes
valid on the rising edge of the serial clock.
V
OUT A/B
(Pins 9, 15):
The Buffered DAC Outputs.
REFHI A/B (Pins 10, 14):
The Reference High Inputs of the
LTC1654. There is a gain of 1 from this pin to the output
in a gain of 1 configuration. In a gain of 1/2 configuration,
there is a gain of 1/2 from this pin to V
OUT
.
REFLO A/B (Pins 11, 13):
The Reference Low Inputs of the
LTC1654.
V
CC
(Pin 16):
The Positive Supply Input. 2.7V
≤
V
CC
≤
5.5V.
Requires a 0.1µF bypass capacitor to ground.
TI I G DIAGRA S
t
2
t
1
SCK
t
9
SDI
X
X
C3
B0
X
X
t
5
CS/LD
t
8
SDO
X
(PREVIOUS
WORD)
X
C3
X
X
X
CURRENT WORD
1654 TD01
4
W
U
U
UW
U
t
6
t
4
t
3
t
7
24-Bit Update (Without Daisy-Chain)
TI I G DIAGRA S
UW
LTC1654
SCK
8
B13
B12
B7
B2
B1
B6
B11
B10
B9
B8
B5
X
B4
B3
B0
X
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
SDI
C3
C2
C1
C0
A3
A2
A1
A0
32-Bit Update (Without Daisy-Chain)
CS/LD
10
12
15
A1
B13
B12
B10
B9
B8
B7
B11
B6
A0
B5
16
22
23
24
25
C0
A3
A2
13
14
17
18
19
20
21
C2
C1
11
26
B4
27
B3
28
B2
29
B1
30
B0
31
X
32
X
SCK
1
2
3
4
5
6
7
8
9
SDI
X
X
X
X
X
X
X
X
C3
32-Bit Update (Can Daisy-Chain)
CS/LD
10
12
15
A1
B13
B12
B12
B11
B11
B13
A1
PREVIOUS WORD
A0
A0
16
C0
C0
A3
A2
A3
A2
13
14
17
18
19
C2
C2
C1
C1
B10
B10
11
20
21
B9
B9
22
B8
B8
23
B7
B7
24
B6
B6
25
B5
B5
26
B4
B4
27
B3
B3
28
B2
B2
29
B1
B1
30
B0
B0
31
X
X
32
X
X
X
CURRENT
WORD
1654 TD02
SCK
1
2
3
4
5
6
7
8
9
SDI
X
X
X
X
X
X
X
X
C3
SDO
X
X
X
X
X
X
X
X
C3
W
CS/LD
5
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