LTC1658
14-Bit Rail-to-Rail
Micropower DAC in MSOP
FEATURES
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s
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s
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DESCRIPTION
The LTC
®
1658 is a single supply, rail-to-rail voltage out-
put, 14-bit digital-to-analog converter (DAC) in an 8-lead
MSOP package. It includes an output buffer amplifier and
an easy-to-use 3-wire cascadable serial interface.
The LTC1658 output swings from 0V to V
REF
. The REF pin
can be tied to V
CC
for rail-to-rail output swing. The LTC1658
operates from a single 2.7V to 5.5V supply. The typical
power supply current is 270µA.
The low power supply current makes the LTC1658 ideal
for battery-powered applications. The space saving MSOP
provides the smallest 14-bit DAC system available.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
s
s
14-Bit Resolution
8-Lead MSOP Package
Buffered True Rail-to-Rail Voltage Output
3V or 5V Single Supply Operation
Very Low Power: I
CC(TYP)
= 270µA
Power-On Reset
3-Wire Cascadable Serial Interface is Compatible
with SPI and MICROWIRE
TM
Maximum DNL Error: 1LSB
Low Cost
APPLICATIONS
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s
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Digital Calibration
Industrial Process Control
Automatic Test Equipment
Cellular Telephones
TYPICAL APPLICATION
Functional Block Diagram: 14-Bit Rail-to-Rail DAC
2.7V TO 5.5V
8
V
CC
2 D
IN
1 CLK
µP
3 CS/LD
16-BIT
SHIFT
REG
AND
DAC
LATCH
14
14-BIT
DAC
6
REF
+
–
V
OUT
7
DNL ERROR (LSB)
RAIL-TO-RAIL
VOLTAGE
OUTPUT
4 D
OUT
TO
OTHER
DACS
POWER-ON
RESET
GND
5
1658 TA01
U
U
U
Differential Nonlinearity
vs Input Code
1.0
0.8
0.6
0.4
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
– 1.0
0
4096
8192
CODE
12288
16383
1658 TA02
1
LTC1658
ABSOLUTE
MAXIMUM
RATINGS
V
CC
to GND .............................................. – 0.5V to 7.5V
TTL Input Voltage .................................... – 0.5V to 7.5V
V
REF
..........................................................– 0.5V to 7.5V
V
OUT
........................................... – 0.5V to (V
CC
+ 0.5V)
Junction Temperature .......................... – 65°C to 125°C
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
CLK
D
IN
CS/LD
D
OUT
1
2
3
4
8
7
6
5
V
CC
V
OUT
REF
GND
LTC1658CMS8
LTC1658IMS8
MS8 PART MARKING
LTCW
LTFW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
JMAX
= 150°C,
θ
JA
= 250°C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
V
CC
= 2.7V to 5.5V, V
OUT
unloaded, REF
≤
V
CC
, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
SYMBOL
DAC
Resolution
Monotonicity
DNL
INL
Differential Nonlinearity
Integral Nonlinearity
Zero Scale Error
V
REF
≤
V
CC
– 0.1V (Note 2)
V
REF
≤
V
CC
– 0.1V (Note 2)
T
A
= 25°C, N8 and S8 Package
T
A
= T
MIN
to T
MAX
, N8 and S8 Package
T
A
= T
MIN
to T
MAX
, MSOP Package
T
A
= 25°C, N8 and S8 Package, (Note 7)
T
A
= T
MIN
to T
MAX
, N8 and S8 Package, (Note 7)
T
A
= T
MIN
to T
MAX
, MSOP Package, (Note 7)
q
q
q
q
q
q
q
q
PARAMETER
CONDITIONS
Offset Error
V
OS
TC
Offset Error Temperature
Coefficient
Gain Error
Gain Error Drift
q
Power Supply
V
CC
I
CC
Positive Supply Voltage
Supply Current
Short-Circuit Current Low
Short-Circuit Current High
For Specified Performance
2.7V
≤
V
CC
≤
5.5V (Note 4)
V
OUT
Shorted to GND
V
OUT
Shorted to V
CC
q
q
Op Amp DC Performance
q
q
2
U
U
W
W W
U
W
(Note 1)
Operating Temperature Range
Commercial ............................................ 0°C to 70°C
Industrial ............................................. –40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
TOP VIEW
CLK 1
D
IN
2
CS/LD 3
D
OUT
4
N8 PACKAGE
8-LEAD PDIP
8
7
6
5
V
CC
V
OUT
REF
GND
ORDER PART
NUMBER
LTC1658CN8
LTC1658IN8
LTC1658CS8
LTC1658IS8
S8 PART MARKING
1658
1658I
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 125°C,
θ
JA
= 100°C/W(N8)
T
JMAX
= 125°C,
θ
JA
= 150°C/W(S8)
MIN
14
14
TYP
MAX
UNITS
Bits
Bits
±1.0
±8.0
1.5
4.0
7.0
±1.5
±4.0
±7.0
±5
±20
±2.5
2.7
270
55
55
5.5
550
120
120
LSB
LSB
mV
mV
mV
mV
mV
mV
µV/°C
LSB
ppm/°C
V
µA
mA
mA
LTC1658
ELECTRICAL CHARACTERISTICS
V
CC
= 2.7V to 5.5V, V
OUT
unloaded, REF
≤
V
CC
, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
SYMBOL
PARAMETER
Output Impedance to GND
Output Line Regulation
AC Performance
Voltage Output Slew Rate
Voltage Output Settling Time
Digital Feedthrough
Reference Input
R
IN
V
REF
Digital I/O
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
OH
V
OL
I
LEAK
C
IN
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage
Digital Input Capacitance
D
IN
Valid to CLK Setup
D
IN
Valid to CLK Hold
CLK High Time
CLK Low Time
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
D
OUT
Output Delay
CLK Low to CS/LD Low
D
IN
Valid to CLK Setup
D
IN
Valid to CLK Hold
CLK High Time
CLK Low Time
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
D
OUT
Output Delay
CLK Low to CS/LD Low
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
C
LOAD
= 15pF
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
C
LOAD
= 15pF
(Note 6)
V
CC
= 5V
V
CC
= 5V
V
CC
= 5V, I
OUT
= – 1mA, D
OUT
Only
V
CC
= 5V, I
OUT
= 1mA, D
OUT
Only
V
CC
= 3V
V
CC
= 3V
V
CC
= 3V, I
OUT
= – 1mA, D
OUT
Only
V
CC
= 3V, I
OUT
= 1mA, D
OUT
Only
V
IN
= GND to V
CC
(Note 6)
q
q
q
q
q
q
q
q
q
q
q
CONDITIONS
Input Code = 0
Input Code = 16383, V
CC
= 2.7V to 5.5V, REF = 2.5V
q
q
MIN
TYP
70
MAX
200
1.5
UNITS
Ω
mV/V
V/µs
µs
nV • s
kΩ
0.35
1.0
12
0.3
(Note 3) to
±0.5LSB
REF Input Resistance
REF Input Range
(Notes 5, 6)
q
q
30
0
2.4
60
V
CC
V
V
0.8
V
CC
– 0.7
0.4
2.0
0.6
V
CC
– 0.7
0.4
±10
10
40
0
40
40
50
40
20
5
20
60
0
60
60
80
60
30
10
30
150
100
V
V
V
V
V
V
V
µA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching (V
CC
= 4.5V to 5.5V)
q
q
q
q
q
q
q
q
q
Switching (V
CC
= 2.7V to 5.5V)
q
q
q
q
q
q
q
q
q
3
LTC1658
ELECTRICAL CHARACTERISTICS
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
a device may be impaired.
Note 2:
Nonlinearity is defined from code 50 to code 16383 (full scale).
See Applications Information.
Note 3:
DAC switched between code 16383 and code 50.
Note 4:
Digital inputs at 0V or V
CC
.
Note 5:
V
OUT
can only swing from (GND +
V
OS
)
to (V
CC
–
V
OS
)
when
output is unloaded. See Applications Information.
Note 6:
Guaranteed by design. Not subject to test.
Note 7:
Measured at code 50.
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL) vs
Input Code
5
4
3
INL ERROR (LSB)
DNL ERROR (LSB)
2
1
0
–1
–2
–3
–4
–5
0
4096
8192
CODE
12288
16383
1658 G01
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4096
8192
CODE
12288
16383
1658 G02
SUPPLY CURRENT (mA)
Minimum Supply Headroom for
Full Output Swing vs Load Current
1.0
OUTPUT PULL-DOWN VOLTAGE (V)
0.9
0.8
0.7
V
CC
– V
OUT
(V)
0.6
0.5
0.4
0.3
0.2
0.1
0
0
5
10
LOAD CURRENT (mA)
15
1658 G04
∆V
OUT
< 1LSB
CODE: ALL 1s
V
OUT
= 4.096V
125°C
OFFSET ERROR (LSB)
4
U W
25°C
–55°C
Differential Nonlinearity (DNL) vs
Input Code
1.0
0.8
0.6
2
3
Supply Current vs Logic Input
Voltage
ALL DIGITAL INPUTS
TIED TOGETHER
1
0
0
1
2
3
4
LOGIC INPUT VOLTAGE (V)
5
1658 G03
Minimum Output Voltage vs
Output Sink Current
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
5
10
OUTPUT SINK CURRENT (mA)
15
1658 G05
Offset Error vs Temperature
0
–0.5
–1.0
CODE: ALL ZEROS
125°C
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–55
–25
5
35
65
TEMPERATURE (°C)
95
125
1658 G06
25°C
–55°C
LTC1658
TYPICAL PERFOR A CE CHARACTERISTICS
Gain Error vs Temperature
5
4
3
GAIN ERROR (LSB)
2
1
0
–1
–2
–3
–4
–5
–55
–25
5
35
65
TEMPERATURE (°C)
95
125
1658 G06
PIN FUNCTIONS
CLK (Pin 1):
The TTL Level Input for the Serial Interface
Clock.
D
IN
(Pin 2):
The TTL Level Input for the Serial Interface
Data. Data on the D
IN
pin is latched into the shift register
on the rising edge of the serial clock and is loaded MSB
first. The LTC1658 requires a 16-bit word to be loaded in.
The last two bits are don’t cares.
CS/LD (Pin 3):
The TTL Level Input for the Serial Inter-
face Enable and Load Control. When CS/LD is low the
CLK signal is enabled, so the data can be clocked in.
When CS/LD is pulled high, data is loaded from the shift
register into the DAC register, updating the DAC output.
D
OUT
(Pin 4):
Output of the Shift Register Which Becomes
Valid on the Rising Edge of the Serial Clock.
GND (Pin 5):
Ground.
REF (Pin 6):
Reference Input. There is a gain of one from
this pin to the output. When tied to V
CC
the output will
swing from GND to V
CC
. The output can only swing to
within it’s offset specification of V
CC
(see Applicatons
Information).
V
OUT
(Pin 7):
Buffered Rail-to-Rail DAC Output.
V
CC
(Pin 8):
Positive Supply Input. 2.7V
≤
V
CC
≤
5.5V.
U W
Broadband Noise
1LSB/DIV
BW = 1Hz TO
100kHz
200µs/DIV
1658 G08
U
U
U
5
FPGA/CPLD
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