Final Electrical Specifications
LTC1662
Ultralow Power, Dual
10-Bit DAC in MSOP
March 2000
FEATURES
s
s
DESCRIPTIO
s
s
s
s
s
s
s
Ultralow Power: 1.5µA (Typ) I
CC
per DAC Plus
0.05µA Sleep Mode for Extended Battery Life
Tiny: Two 10-Bit DACs in an 8-Lead MSOP—
Half the Size of an SO-8
Wide 2.7V to 5.5V Supply Range
Double Buffered for Simultaneous DAC Updates
Rail-to-Rail Voltage Outputs Drive 1000pF
Reference Range Includes Supply for Ratiometric
0V-to-V
CC
Output
Reference Input Impedance Is Code-Independent
(7.1MΩ Typ)—Eliminates External Buffers
3-Wire Serial Interface with
Schmitt Trigger Inputs
Differential Nonlinearity:
±0.75LSB
Max
The LTC
®
1662 is an ultralow power, fully buffered volt-
age output, dual 10-bit digital-to-analog converter (DAC).
Each DAC draws just 1.7µA (typ) total supply-plus-
reference operating current, yet is capable of supplying
DC output currents in excess of 1mA and reliably driving
capacitive loads of up to 1000pF. A programmable Sleep
mode further reduces total operating current to a negli-
gible 0.05µA.
Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent lin-
earity while allowing for an exceptionally small external
form factor. The double-buffered input logic provides
simultaneous update capability and can be used to write to
either DAC without interrupting Sleep mode.
With its ultralow operating current and exceptionally
small size, the LTC1662 is ideal for use in battery-
powered products.
The LTC1662 is pin- and software-compatible with the
LTC1661 micropower dual 10-bit DAC. It is available in
8-pin MSOP and PDIP packages and is specified over the
industrial temperature range.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s
s
s
s
s
Mobile Communications
Portable Battery-Powered Instruments
Remote Industrial Devices
Digitally Controlled Amplifiers and Attenuators
Automatic Calibration for Manufacturing
BLOCK DIAGRA
V
OUT A
8
GND
7
V
CC
6
V
OUT B
5
TOTAL OPERATING CURRENT (µA)
LATCH
LATCH
LATCH
LATCH
10-BIT
DAC A
10-BIT
DAC B
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
1
CS/LD
2
SCK
3
D
IN
4
REF
1662 BD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.5
V
REF
= V
CC
T
A
= 25°C
3.0
3.5
W
U
Total Supply-Plus-Reference
Operating Current
CODE = 1023
CODE = 512
CODE = 0
4.0
V
CC
(V)
4.5
5.0
5.5
1662 G01
1
LTC1662
ABSOLUTE
(Note 1)
AXI U
RATI GS
Operating Temperature Range
LTC1662C ............................................. 0°C to 70°C
LTC1662I ........................................... – 40°C to 85°C
Lead Temperature (Soldering, 10 sec)................ 300°C
V
CC
to GND .............................................. – 0.3V to 7.5V
Logic Inputs to GND ................................ – 0.3V to 7.5V
V
OUT A
, V
OUT B
, REF to GND ......... – 0.3V to (V
CC
+ 0.3V)
Maximum Junction Temperature ......................... 125°C
Storage Temperature Range ................ – 65°C to 150°C
PACKAGE/ORDER I FOR ATIO
TOP VIEW
CS/LD
SCK
D
IN
REF
1
2
3
4
8
7
6
5
V
OUT A
GND
V
CC
V
OUT B
ORDER PART
NUMBER
CS/LD 1
LTC1662CMS8
LTC1662IMS8
MS8 PART MARKING
LTKB
LTKC
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 150°C/W
Consult factory for Military grade parts.
The
q
denotes the specifications which apply over the full operating
temperature range (T
A
= T
MIN
to T
MAX
), otherwise specifications are at T
A
= 25°C. V
CC
= 2.7V to 5.5V, V
REF
≤
V
CC
, V
OUT
Unloaded
unless otherwise noted.
SYMBOL
Accuracy
Resolution
Monotonicity
DNL
INL
V
OS
V
OS
TC
GE
GE TC
PSR
Differential Nonlinearity
Integral Nonlinearity
Offset Error
V
OS
Temperature Coefficient
Gain Error
Gain Error Temperature
Coefficient
Power Supply Rejection
Input Voltage Range
Input Resistance
Input Capacitance
Active Mode
Sleep Mode
V
REF
= 2.5V
q
q
q
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
(Note 2)
(Note 2)
(Note 2)
V
CC
= 5V, V
REF
= 4.096V, Measured at Code 20
V
CC
= 5V, V
REF
= 4.096V
Reference Input
0
3.9
7.1
2.5
10
V
CC
V
MΩ
GΩ
pF
2
U
U
W
W W
U
W
TOP VIEW
8
7
6
5
V
OUT A
GND
V
CC
V
OUT B
ORDER PART
NUMBER
LTC1662CN8
LTC1662IN8
SCK 2
D
IN
3
REF 4
N8 PACKAGE
8-LEAD PLASTIC DIP
T
JMAX
= 125°C,
θ
JA
= 100°C/W
MIN
10
10
TYP
MAX
UNITS
Bits
Bits
q
q
q
q
±0.12
±0.8
±5
±15
±1
±12
0.18
±0.75
±4
±25
±8
LSB
LSB
mV
µV/°C
LSB
µV/°C
LSB/V
q
LTC1662
The
q
denotes the specifications which apply over the full operating
temperature range (T
A
= T
MIN
to T
MAX
), otherwise specifications are at T
A
= 25°C. V
CC
= 2.7V to 5.5V, V
REF
≤
V
CC
, V
OUT
Unloaded
unless otherwise noted.
SYMBOL
V
CC
I
CC
PARAMETER
Positive Supply Voltage
Supply Current
CONDITIONS
For Specified Performance
V
CC
= 3V (Note 3)
V
CC
= 5V (Note 3)
V
CC
= 3V (Note 3)
V
CC
= 5V (Note 3)
q
ELECTRICAL CHARACTERISTICS
MIN
2.7
TYP
MAX
5.5
UNITS
V
µA
µA
µA
µA
µA
µA
mA
mA
V/ms
V/ms
ms
ms
pF
V
V
Power Supply
3.0
3.5
q
q
4.0
4.5
5.0
5.5
0.10
0.18
70
80
Sleep Mode Operating Current Supply Plus Reference Current, V
CC
= V
REF
= 5V, (Note 3)
q
0.05
DC Performance
Short-Circuit Current Low
Short-Circuit Current High
AC Performance
Voltage Output Slew Rate
Voltage Output Settling Time
Capacitive Load Driving
Digital I/O
V
IH
V
IL
I
LK
C
IN
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Leakage
Digital Input Capacitance
V
CC
= 2.7V to 5.5V
V
CC
= 2.7V to 3.6V
V
CC
= 4.5V to 5.5V
V
CC
= 2.7V to 5.5V
V
IN
= GND to V
CC
(Note 6)
q
q
q
q
q
V
OUT
= 0V, V
CC
= V
REF
= 5V, Code = 1023 (Note 7)
V
OUT
= V
CC
= V
REF
= 5V, Code = 0 (Note 7)
Rising (Notes 4, 5)
Falling (Notes 4, 5)
0.1V
FS
to 0.9V
FS
±0.5LSB
(Notes 4, 5)
0.9V
FS
to 0.1V
FS
±0.5LSB
(Notes 4, 5)
q
q
5
3
12
10
20
7
0.40
0.75
1000
2.4
2.0
0.8
0.6
±0.05
1.5
±1.0
V
V
µA
pF
TI I G CHARACTERISTICS
range, otherwise specifications are at T
A
= 25°C.
PARAMETER
D
IN
Valid to SCK Setup
D
IN
Valid to SCK Hold
SCK High Time
SCK Low Time
CS/LD Pulse Width
LSB SCK High to CS/LD High
CS/LD Low to SCK High
SCK Low to CS/LD Low
CS/LD High to SCK Positive Edge
SCK Frequency
V
CC
= 2.7V to 5.5V
t
1
t
2
t
3
t
4
D
IN
Valid to SCK Setup
D
IN
Valid to SCK Hold
SCK High Time
SCK Low Time
SYMBOL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
9
t
11
V
CC
= 4.5V to 5.5V
UW
The
q
denotes the specifications which apply over the full operating temperature
MIN
q
q
CONDITIONS
TYP
15
– 10
14
14
27
2
– 21
–5
0
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
0
30
30
100
30
20
0
20
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
Square Wave (Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
q
q
q
q
q
q
q
q
q
q
q
q
16.7
75
0
50
50
20
– 10
15
15
MHz
ns
ns
ns
ns
3
LTC1662
TI I G CHARACTERISTICS
range, otherwise specifications are at T
A
= 25°C.
PARAMETER
CS/LD Pulse Width
LSB SCK High to CS/LD High
CS/LD Low to SCK High
SCK Low to CS/LD Low
CS/LD High to SCK Positive Edge
SCK Frequency
SYMBOL
t
5
t
6
t
7
t
9
t
11
Note 1:
Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2:
Nonlinearity and monotonicity are defined and tested at V
CC
= 5V,
V
REF
= 4.096V, from code 20 to code 1023. See Figure 2.
Note 3:
Digital inputs at 0V or V
CC
.
TI I G DIAGRA
SCK
t
9
D
IN
t
5
CS/LD
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL)
4
INTEGRAL NONLINEARITY (LSB)
3
2
1
0
–1
–2
–3
–4
0
256
512
CODE
768
1023
1662 G02
DIFFERENTIAL NONLINEARITY (LSB)
4
U W
W
UW
UW
The
q
denotes the specifications which apply over the full operating temperature
CONDITIONS
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
Square Wave (Note 6)
q
q
q
q
q
q
MIN
150
50
30
0
30
TYP
30
3
– 14
–5
0
MAX
UNITS
ns
ns
ns
ns
ns
10
MHz
Note 4:
Load is 10kΩ in parallel with 100pF.
Note 5:
V
CC
= V
REF
= 5V. DAC switched between 0.1V
FS
and 0.9V
FS
; i.e.,
codes k = 102 and k = 922.
Note 6:
Guaranteed by design, not subject to test.
Note 7:
One DAC output loaded.
t
1
t
2
t
3
t
4
t
6
t
11
A3
t
7
A2
A1
X1
X0
1662 TD
Differential Nonlinearity (DNL)
0.75
0.60
0.40
0.20
0
–0.20
–0.40
–0.60
– 0.80
0
256
512
CODE
768
1023
1662 G03
LTC1662
OPERATIO
SCK
D
IN
CS/LD
Table 1. DAC Control Functions
CONTROL
A3 A2 A1 A0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
No Change
Load DAC A
INPUT REGISTER
STATUS
No Change
Load DAC A
Load DAC B
DAC REGISTER
STATUS
No Update
No Update
No Update
Reserved
Reserved
Reserved
Reserved
Reserved
Update Outputs
Update Outputs
Wake
Wake
Load Both DAC Regs with Existing Contents of Input
Regs. Outputs Update. Part Wakes Up
Load Input Reg A. Load DAC Regs with New Contents
of Input Reg A and Existing Contents of Reg B. Outputs
Update. Part Wakes Up
Load Input Reg B. Load DAC Regs with Existing Contents
of Input Reg A and New Contents of Reg B. Outputs
Update. Part Wakes Up
POWER-DOWN STATUS
(SLEEP/WAKE)
No Change
No Change
No Change
COMMENTS
No Operation. Power-Down Status Unchanged
(Part Stays In Wake or Sleep Mode)
Load Input Register A with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
Load Input Register B with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
No Change
No Change
Load DACs A, B
with Same
10-Bit Code
U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
CONTROL CODE
INPUT CODE
INPUT WORD W
0
(SCK ENABLED)
(INSTRUCTION
EXECUTED)
1662 F01
DON’T CARE
Figure 1. Register Loading Sequence
Load DAC B
Update Outputs
Wake
Reserved
Reserved
No Update
No Update
Update Outputs
Wake
Sleep
Wake
Part Wakes Up. Input and DAC Regs Unchanged. DAC
Outputs Reflect Existing Contents of DAC Regs
Part Goes to Sleep. Input and DAC Regs Unchanged. DAC
Outputs Set to High Impedance State
Load Both Input Regs. Load Both DAC Regs with New
Contents of Input Regs. Outputs Update. Part Wakes Up
5
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