The UT54ACTS220 is designed to be a companion chip to
UTMC’s UT69151 SμMMIT family for the purpose of gener-
ating clock and wait-state signals. The device contains a divide
by two circuit that accepts TTL input levels and drives CMOS
output buffers. The chip accepts a 48MHz clock and generates
a 24MHz clock. The 48MHz clock can have a duty cycle that
varies by
±
20%. The UT54ACT220 generates a 24MHz clock
with a
±
5% duty cycle variation. The wait-state circuit generates
a single wait-state by delaying the falling edge of DTACK into
the SμMMIT. The clock/timing device generates DTACK from
the falling edge of input RCS which is synchronized by the fall-
ing edge of 24MHz. The SμMMIT drives inputs RCS and
DMACK.
The devices are characterized over full military temperature
range of -55°C to +125°C.
LOGIC SYMBOL
MRST
48MHz
RCS
DMACK
(10)
(6)
(9)
(8)
S
CTR1
SRG2
1D
S
(11)
(12)
DTACK
(13)
PINOUTS
14-Pin DIP
Top View
NC
CLKOUT
CLKOUT
CLKIN
NC
48MHz
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
24MHz
DTACK
TEST
MRST
RCS
DMACK
14-Lead Flatpack
Top View
NC
CLKOUT
CLKOUT
CLKIN
NC
48MHz
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
24MHz
DTACK
TEST
MRST
RCS
DMACK
24MHz
TEST
(2)
CLKIN
(4)
(3)
CLKOUT
CLKOUT
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
1
PIN DESCRIPTION
Pin Number
2
3
4
6
8
9
10
11
12
13
Pin Name
CLKOUT
CLKOUT
CLKIN
48MHz
DMACK
RCS
MRST
TEST
DTACK
24MHz
Buffered version of CLKIN.
Inverted version of CLKIN.
Clock Input. This signal can be any arbitrary signal that the user wishes to buffer.
48MHz Clock. The 24MHz clock is created by dividing this signal by two.
DMA Acknowledge. This input is generated by the SμMMIT. When high, this signal will
cause DTACK output to be forced high.
RAM Chip Select. This input is generated by the SμMMIT.
Master Reset. This input can be used to preset 24MHz, DTACK and TEST. For normal
operation tie MRST to V
DD
through a resistor.
Test output signal.
Data Transfer Acknowledge. This signal can be used to drive the DTACK signal of the
SμMMIT if the user requires one wait state during the memory transfer.
24MHz Clock. This output runs at half the frequency of the 48MHz input. The falling
edge of 24MHz is the signal that latches the DTACK outputs. 24MHz is forced high
whenever MRST is low. Properly loaded, 24MHz will have a 50% duty cycle
±
5%.
Description
FUNCTIONAL TIMING: Single SμMMIT Wait-State
For both read and write memory cycles, DTACK is an input to the SμMMIT E and SμMMIT LXE/DXE. A non-wait state memory
requires two clock cycles, T
1
and T
2
of figure 1. For accessing slower memory devices, the UT54ACTS220 holds DTACK to a log-
ical “1”. This results in the stretching of memory cycles by one clock to three clock cycles, T
W
of figure 1. The SμMMIT E and
SμMMIT LXE/DXE samples the DTACK on the rising edge of the 24 MHz clock. If DTACK is not generated before the rising
edge of the clock, the SμMMIT E and SμMMIT LXE/DXE extends the memory cycle.
48MHz
24MHz
T
1
T
W
T
2
DMACK
RCS
DTACK
Figure 1. Functional Timing
2
LOGIC DIAGRAM
24MHz
D
Q
D
Q
DTACK
48MHz
MRST
RCS
CK Q
RST
CK Q
PRE
D
CK
Q
PRE
Q
TEST
DMACK
CLKIN
CLKOUT
CLKOUT
3
OPERATIONAL ENVIRONMENT
PARAMETER
Total Dose
SEU Threshold
1
SEL Threshold
Neutron Fluence
2
Notes:
1. Device storage elements are immune to SEU affects.
2. Not tested, inherent of CMOS technology.
LIMIT
1.0E6
80
>120
1.0E14
UNITS
rad(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-0.3 to V
DD
+0.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
48MHz
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
Duty Cycle
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
50
±
20%
UNITS
V
V
°C
MHz
4
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V
±
10%; V
SS
= 0V
6
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
从全球来看，智能电视在设备互联接口、内容服务接口、应用程序开发接口、系统安全可信技术等方面的标准尚未统一，厂商采用不同的操作系统和内容接口，各自的应用互不兼容，对产业整体发展造成障碍，在应用丰富度上也很欠缺。近日国内一些家电厂商主办智能电视开发论坛，力图吸引更多的开发者参与进来，从这一点来看，目前还是家电厂商较为主动地在推动智能电视标准化以及各类应用的开发。 TV OS成产业角逐焦点 ...[详细]
东芝光电继电器TLP3547评测
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
