SLGSSTU32864E
DDR2 Configurable Registered Buffer
Features:
• Compatible with JEDEC standard SSTU32864
• Differential Clock inputs
• SSTL_18 Clock and data input signaling
• Output circuitry minimizes effects of SSO
and unterminated lines
• LVCMOS input levels on control and RESET pins
• 1.7V-1.9V Supply voltage range.
• Max Clock frequency > 300MHz
General Description
The SLGSSTU32864 is a configurable registered buffer designed for 1.7V to 1.9V VDD operating range.
When C1 input pin is low, the SLGSSTU32864 is 1:1 25-bit configuration. When C1 input pin is high, the
SLGSSTU32864 is 1:2 14-bit configuration. Additionally, C0 input pin controls the 1:2 pinout as register-A
configuration (if low) , and register-B configuration (if high). The C0,C1, and RESET pins are LVCMOS
input levels.The C0,C1 input pins are not intended to be switched dynamically during normal operation.
They should be tied to logic high or low levels to configure the register.
Data propagation from D to Q is controlled by the differential clock (CLK/CLK) and a control signals. The
rising edge of CLK (crossing with CLK falling) is used to register the Data. All inputs are SSTL_18 except
C0,C1, and RESET pins.
The SLGSSTU32864 supports low-power standby operation. Setting RESET pin to a logic “low” disables
(CLK/CLK) receivers, and allows floating inputs to all other receivers as well (D, V
REF
, CLK/CLK). Addi-
tionally, all internal registers are reset, and outputs (Q) are set “low”. RESET input pin must always be
driven to a valid logic state “high” or “low”.
RESET, an LVCMOS asynchronous signal, is also intended for use at the time of power-up. RESET must
be held at a logic “low” level during power up. This ensures defined outputs before a stable CLK/CLK is
supplied.
The SLGSSTU32864 supports low-power active operation as it monitors DCS and CSR inputs. The Qn
outputs will be prevented from changing states when both DCS and CSR inputs are high. The Qn outputs
will be allowed to change state if either one of DCS or CSR inputs is low. If DCS control is not desired,
then CSR input should be held low. In that case, the setup and hold times of DCS is the same as the other
D inputs.
Ordering Information:
Package type
LFBGA-96ball
13.5 X 5.5 mm body
LFBGA-96ball
13.5 X 5.5 mm body
Package suffix
X
X
Topside marking
SLGSSTU32864EX
SLGSSTU32864EX
Ordering code
SLGSSTU32864EX-TR
(2,000 pcs/tape and reel)
SLGSSTU32864EX (2,000
pcs/tray)
Applications:
• PC3200/4300 DDR2 memory modules
• 1:1 25-bit or 1:2 14-bit configurable registered
buffer
• 1.8V data registers
Silego Technology Inc.
(408) 327-8800
1
PRELIMINARY
Data is subject to change.
Mar 5, 2004
SLGSSTU32864E
SLGSSTU32864 Terminal Description:
TERMINAL
NAME
Q (1:25)
GND
VDD
D (1:25)
CLK
CLK
C0,C1
RESET
VREF
CSR, DCS
DODT
DCKE
QCS
QODT
QCKE
NC
DNU
ZOL,ZOH
TYPE
OUTPUT
GROUND
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
NC
DNU
NC
DESCRIPTION
Q-Outputs that are stopped by CSR & DCS control.
Ground
Supply voltage
D-Inputs latched in on the rising edge of CLK crossing falling edge of CLK
Positive clock input
Negative clock input
Control inputs for register configurations: 1:1 , 1:2 A , 1:2 B
Asynchronous reset (active low)
Input reference voltage. Both inputs are internally connected together by 200Ω
Chip select control pins. Q1-Q25 outputs stopped when CSR & DCS=high
D-input. This register not stopped by CSR & DCS control.
D-input. This register not stopped by CSR & DCS control.
Q-Output. Not stopped by CSR & DCS control.
Q-Output. Not stopped by CSR & DCS control.
Q-Output. Not stopped by CSR & DCS control.
No-connect. Ball present, but no internal connection to the die.
Do-not-use. Ball internally connected to the die and should be left open-circuit.
Reserved for future use. Ball present, not electrically connected to the die.
Function Table
Inputs
RESET
H
H
H
H
H
H
H
H
H
H
H
H
L
DCS
L
L
L
L
L
L
H
H
H
H
H
H
X, or
Floating
CSR
L
L
L
H
H
H
L
L
L
H
H
H
X, or
Floating
L or H
X, or
Floating
L or H
X, or
Floating
L or H
L or H
L or H
L or H
L or H
L or H
CLK
CLK
Dn,DODT
, DCKE
L
H
X
L
H
X
L
H
X
L
H
X
X, or
Floating
Qn
L
H
Q
0
L
H
Q
0
L
H
Q
0
Q
0
Q
0
Q
0
L
Outputs
QCS
L
L
Q
0
L
L
Q
0
H
H
Q
0
H
H
Q
0
L
QODT,
QCKE
L
H
Q
0
L
H
Q
0
L
H
Q
0
L
H
Q
0
L
Silego Technology Inc.
(408) 327-8800
5
PRELIMINARY
Data is subject to change.
Mar 5, 2004
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