PRELIMINARY
CY9C62256
32K x 8 Magnetic Nonvolatile CMOS RAM
Features
• 100% Form, Fit, Function - compatible with 32K × 8,
micropower SRAM (CY62256).
— Fast Read and Write access: 70 ns
— Voltage range: 4.5V–5.5V operation
— Low active power: 330 mW (max.)
—
Low standby power, CMOS: 495
µW
(max.)
—
Data retention current: 0
µA
at V
CC
= 0V
— Easy memory expansion with CE and OE features
— TTL-compatible inputs and outputs
— Automatic power-down when deselected
• Replaces 32K × 8 Battery Backed (BB)SRAM, SRAM,
EEPROM, FeRAM or Flash memory
— Data is automatically Write protected during power
loss
— Write Cycles Endurance: > 10
15
Cycles
— Data Retention: > 10 Years
— Shielded from external magnetic fields
— Extra 64 Bytes for Device Identification and tracking
— Optional industrial temperature range: –40°C to
+85°C
• JEDEC STD 28-pin DIP (600-mil), 28-pin (300-mil) SOIC
and TSOP packages
Functional Description
The CY9C62256 is a high-performance CMOS nonvolatile
RAM employing an advanced magnetic RAM (MRAM)
process. An MRAM is nonvolatile memory that operates as a
fast read and write RAM. It provides data retention for more
than ten years while eliminating the reliability concerns,
functional disadvantages and system design complexities of
battery-backed SRAM, EEPROM, Flash and FeRAM. Its fast
writes and high write cycle endurance makes it superior to
other types of nonvolatile memory.
The CY9C62256 operates very similarly to SRAM devices.
Memory read and write cycles require equal times. The MRAM
memory is nonvolatile due to its unique magnetic process.
Unlike BBSRAM, the CY9C62256 is truly a monolithic nonvol-
atile memory. It provides the same functional benefits of a fast
write without the serious disadvantages associated with
modules and batteries or hybrid memory solutions.
These capabilities make the CY9C62256 ideal for nonvolatile
memory applications requiring frequent or rapid writes in a
bytewide environment.
The CY9C62256 is offered in both commercial and industrial
temperature ranges.
Logic Block Diagram
Pin Configurations
SOIC/DIP
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
INPUTBUFFER
A
11
A
10
A
9
A
8
A
7
A
6
A
3
A
2
A
1
CE
WE
OE
A
5
A
4
A
14
A
13
A
12
A
0
ROW DECODER
I/O
0
I/O
1
SENSE AMPS
Silicon Sig.
512x512
Y
ARRA
I/O
2
I/O
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
21
20
19
18
17
16
15
14
13
12
11
10
9
8
I/O
4
I/O
5
POWER
COLUMN
DECODER
DOWN &
WRITE
PROTECT
I/O
6
I/O
7
TSOP I
Top View
(not to scale)
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
Cypress Semiconductor Corporation
Document #: 38-15001 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised March 22, 2004
PRELIMINARY
Overview
The CY9C62256 is a byte wide MRAM memory. The memory
array is logically organized as 32,768 x 8 and is accessed
using an industry standard parallel asynchronous SRAM-like
interface. The CY9C62256 is inherently nonvolatile and offers
write protect during sudden power loss. Functional operation
of the MRAM is similar to SRAM-type devices, otherwise.
Memory Architecture
Users access 32,768 memory locations each with 8 data bits
through a parallel interface. Internally, the memory array is
organized into 8 blocks of 512 rows x 64 columns each.
The access and cycle time are the same for read and write
memory operations. Unlike an EEPROM or Flash, it is not
necessary to poll the device for a ready condition since writes
occur at bus speed.
Memory Operation
The CY9C62256 is designed to operate in a manner similar to
other bytewide memory products. For users familiar with
BBSRAM, the MRAM performance is superior. For users
familiar with EEPROM, Flash and FeRAM, the obvious differ-
ences result from higher write performance of MRAM
technology and much higher write endurance.
All memory array bits are set to logic “1” at the time of
shipment.
Read Operation
A read cycle begins whenever WE (Write Enable bar) is
inactive (HIGH) and CE (Chip Enable bar) and OE (Output
Enable bar) are active LOW. The unique address specified by
the 15 address inputs (A0–A14) defines which of the 32,768
bytes of data is to be accessed. Valid data will be available at
the eight output pins within t
AA
(access time) after the last
address input is stable, providing that CE and OE access times
are also satisfied. If CE and OE access times are not satisfied
then the data access must be measured from the
later-occurring signal (CE or OE) and the limiting parameter is
either t
ACE
for CE or t
DOE
for the OE rather than address
access.
Write Cycle
The CY9C62256 initiates a write cycle whenever the WE and
CE signals are active (LOW) after address inputs are stable.
The later occurring falling edge of CE or WE will determine the
start of the write cycle. The write cycle is terminated by the
earlier rising edge of CE or WE. All address inputs must be
kept valid throughout the write cycle. The OE control signal
should be kept inactive (HIGH) during write cycles to avoid bus
contention. However, if the output drivers are enabled (CE and
OE active) WE will disable the outputs in t
HZWE
from the WE
falling edge.
Unlike other nonvolatile memory technologies, there is no
write delay with MRAM. The entire memory operation occurs
in a single bus cycle. Therefore, any operation including read
or write can occur immediately following a write. Data Polling,
a technique used with EEPROMs to determine if the write is
complete is unnecessary. Page write, a technique used to
enhance EEPROM write performance is also unnecessary
because of inherently fast write cycle time for MRAM.
CY9C62256
Write Inhibit and Data Retention Mode
This feature protects against the inadvertent write. The
CY9C62256 provides full functional capability for V
CC
greater
than 4.5V and write protects the device below 4.0V. Data is
maintained in the absence of V
CC
. During the power-up,
normal operation can resume 20
µs
after V
PFD
is reached.
Refer to page 8 for details.
Sudden Power Loss—“Brown Out”
The nonvolatile RAM constantly monitors V
CC
. Should the
supply voltage decay below the operating range, the
CY9C62256 automatically write-protects itself, all inputs
become don’t care, and all outputs become high-impedance.
Refer to page 8 for details.
Silicon Signature/Device ID
An extra 64 bytes of MRAM are available to the user for Device
ID. By raising A9 to V
CC
+ 2.0V and by using address locations
00(Hex) to 3F(Hex) on address pins A7, A6, A14, A13, A12 &
A0 (MSB to LSB) respectively, the additional Bytes may be
accessed in the same manner as the regular memory array,
with 140 ns access time. Dropping A9 from input high
(V
CC
+ 2.0V) to < V
CC
returns the device to normal operation
after 140-ns delay.
Address (MSB to LSB)
A7 A6 A14 A13 A12 A0
00h
01h
02h – 3Fh
Description
Manufacturer ID
Device ID
User Space
ID
34h
40h
62 Bytes
All User Space bits above are set to logic “1” at the time of
shipment.
Magnetic Shielding
CY9C62256 is protected from external magnetic fields through
the application of a “magnetic shield” that covers the entire
memory array.
Applications
Battery-Backed SRAM (BB SRAM) Replacement
CY9C62256 is designed to replace (plug and play) existing
BBSRAM while eliminating the need for battery and V
CC
monitor IC, reducing cost and board space and improving
system reliability.
The cost associated with multiple components and assemblies
and manufacturing overhead associated with battery-backed
SRAM is eliminated by using monolithic MRAM. CY9C62256
eliminates multiple assemblies, connectors, modules, field
maintenance and environmental issues common with BB
SRAM. MRAM is a true nonvolatile RAM with high perfor-
mance, high endurance, and data retention.
Battery-backed SRAMs are forced to monitor V
CC
in order to
switch to the backup battery. Users that are modifying existing
designs to use MRAM in place of BB SRAM, can eliminate the
V
CC
controller IC along with the battery. MRAM performs this
function on chip.
Cost:
The cost of both the component and manufacturing
overhead of battery-backed SRAM is high. In addition, there is
a built in rework step required for battery attachment in case
Document #: 38- 15001 Rev. *C
Page 2 of 11
PRELIMINARY
of surface mount assembly. This can be eliminated with
MRAM. In case of DIP battery backed modules, the assembly
techniques are constrained to through-hole assembly and
board wash using no water.
System Reliability:
Battery-backed SRAM is inherently
vulnerable to shock and vibration. In addition, a negative
voltage, even a momentary undershoot, on any pin of a
battery-backed SRAM can cause data loss. The negative
voltage causes current to be drawn directly from the battery,
weakens the battery, and reduces its capacity over time. In
general, there is no way to monitor the lost battery capacity.
MRAM guarantees reliable operation across the voltage range
with inherent nonvolatility.
Space:
Battery-backed SRAM in DIP modules takes up board
space height and dictates through-hole assembly. MRAM is
offered in surface mount as well as DIP packages.
Field Maintenance:
Batteries must eventually be replaced
and this creates an inherent maintenance problem. Despite
projections of long life, it is difficult to know how long a battery
will last, considering all the factors that degrade them.
Environmental:
Lithium batteries are a potential disposal
burden and considered a fire hazard. MRAM eliminates all
such issues through a truly monolithic nonvolatile solution.
Users replacing battery-backed SRAMs with integrated Real
Time Clock (RTC) in the same package may need to move
RTC function to a different location within the system.
EEPROM Replacement
CY9C62256 can also replace EEPROM in current applica-
tions. CY9C62256 is pinout and functionally compatible to
CY9C62256
bytewide EEPROM, however it does not need data-bar polling,
page write and hardware write protect due to its fast write and
inadvertent write protect features.
Users replacing EEPROMs with MRAM can eliminate the
page mode operation and simplify to standard asynchronous
write. Additionally, data-bar polling can be eliminated, since
every byte write is completed within same cycle. All writes are
completed within 70 ns.
FeRAM Replacement
FeRAM requires addresses to be latched on falling edge of
CE, which adds to system overhead in managing the CE and
latching function. MRAM eliminates this overhead by offering
a simple asynchronous SRAM interface.
Users replacing FeRAM can simplify their address decoding
since CE does not need to be driven active and then inactive
for each address. This overhead is eliminated when using
MRAM.
Secondly, MRAM read is nondestructive and no precharge
cycle is required like the one used with FeRAM.This has no
apparent impact to the design, however the read cycle time
can now see immediate improvement equal to the precharge
time.
Boot-up PROM (EPROM, PROM) Function Replacement
The CY9C62256 can be accessed like an EPROM or PROM.
When CE and OE are low and WE is high, the data stored at
the memory location determined by the address pins is
asserted on the outputs. MRAM may be used to accomplish
system boot up function using this condition.
Document #: 38- 15001 Rev. *C
Page 3 of 11
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................... –40°C to +85°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................–0.5V to V
CC
+ 0.5V
except in case of Super Voltage pin (A9) while accessing 64
device ID and Silicon signature Bytes.........−0.5V to V
CC
+ 2.5V
Output Current into Outputs (LOW) .............................20 mA
CY9C62256
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Maximum Exposure to Magnetic
Field
[2]
:.................................................... (@Device package)
Operating Conditions................................................ < 20 Oe
Non-operating Conditions
[3]
:..................................... < 50 Oe
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
CY9C62256-70
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX[4]
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply Current
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
−
0.3V
V
IN
> V
CC
−
0.3V
or V
IN
< 0.3V, f = 0
Test Conditions
V
CC
= Min., I
OH
=
−1.0
mA
V
CC
= Min., I
OL
= 2.1 mA
2.2
–0.5
[1]
–0.5
–0.5
Min.
2.4
0.4
V
CC
+ 0.5V
0.8
+0.5
+0.5
60
Typ.
[5]
Max.
Unit
V
V
V
V
µA
µA
mA
I
SB1
Automatic CE
Power-down Current—
TTL Inputs
Automatic CE
Power-down Current—
CMOS Inputs
500
µA
µA
I
SB2
90
Capacitance
[6]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
6
8
Unit
pF
pF
Notes:
1. V
IL
(min.) = –2.0V for pulse duration of 20 ns.
2. Magnetic field exposure is highly dependent on the distance from the magnetic field source. The magnetic field falls off as 1/R squared, where R is the distance
from the magnetic source.
3. Exposure beyond this level may cause loss of data. Non-operating conditions refer to storage, transport, etc.
4. I
IX
during access to 64 device ID and silicon signature bytes with super voltage pin at V
CC
+ 2.0V will be 100
µ
A max.
5. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(T
A
= 25°C, V
CC
). Parameters are guaranteed by design and characterization, and not 100% tested.
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38- 15001 Rev. *C
Page 4 of 11
PRELIMINARY
AC Test Loads and Waveforms
R1 1800
Ω
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
R2
990Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
990Ω
3.0V
10%
GND
< 5 ns
Equivalent to:
R1 1800
Ω
CY9C62256
ALL INPUT PULSES
90%
90%
10%
< 5 ns
(a)
(b)
THÉ
VENIN EQUIVALENT
639Ω
OUTPUT
1.77V
Switching Characteristics
Over the Operating Range
[7]
CY9C62256-70
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Cycle
[10,11]
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[8, 9]
WE HIGH to Low Z
[8]
5
70
60
60
0
0
50
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[8]
OE HIGH to High Z
[8,9]
CE LOW to Low Z
[8]
CE HIGH to High Z
[8,9]
CE LOW to Power-up
CE HIGH to Power-down
0
70
5
25
5
25
5
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Unit
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write pulse width for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38- 15001 Rev. *C
Page 5 of 11
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