D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
CY7C09269V/79V/89V
CY7C09369V/79V/89V
3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
Features
■
■
■
True dual-ported memory cells that allow simultaneous access
of the same memory location
Six flow through/pipelined devices:
❐
16K x 16/18 organization (CY7C09269V/369V)
❐
32K x 16/18 organization (CY7C09279V/379V)
❐
64K x 16/18 organization (CY7C09289V/389V)
Three modes:
❐
Flow through
❐
Pipelined
❐
Burst
Pipelined output mode on both ports allows fast 100 MHz
operation
0.35 micron CMOS for optimum speed and power
High speed clock to data access: 6.5
[1, 2]
, 7.5
[2]
, 9, 12 ns (max)
3.3V low operating power:
❐
Active = 115 mA (typical)
❐
Standby = 10
μA
(typical)
Fully synchronous interface for easier operation
Burst counters increment addresses internally:
❐
Shorten cycle times
❐
Minimize bus noise
❐
Supported in flow through and pipelined modes
Dual chip enables easy depth expansion
Upper and lower byte controls for bus matching
Automatic power down
Commercial and industrial temperature ranges
Pb-Free 100-pin TQFP package available
■
■
■
■
■
■
■
■
■
■
■
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
0L
CE
1L
LB
L
OE
L
1
0/1
1
0/1
0
0
CE
0R
CE
1R
LB
R
OE
R
FT/Pipe
L
I/O
8/9L
–I/O
15/17L
[4]
8/9
14/15/16
0/1
1b 0b 1a 0a
b
a
0a 1a 0b 1b
a
b
0/1
FT/Pipe
R
8/9
[3]
8/9
I/O
8/9R
–I/O
15/17R
I/O
Control
I/O
Control
8/9
14/15/16
[3]
[4]
I/O
0L
–I/O
7/8L
A
0L
–A
13/14/15L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
[5]
I/O
0R
–I/O
7/8R
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
A
0R
–A
13/14/15R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
[5]
True Dual-Ported
RAM Array
Notes
1. Call for availability.
2. See page 6 for Load Conditions.
3. I/O
8
–I/O
15
for x16 devices; I/O
9
–I/O
17
for x18 devices.
4. I/O
0
–I/O
7
for x16 devices. I/O
0
–I/O
8
for x18 devices.
5. A
0
–A
13
for 16K; A
0
–A
14
for 32K; A
0
–A
15
for 64K devices.
Cypress Semiconductor Corporation
Document #: 38-06056 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 25, 2009
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Pinouts
Figure 1. 100-Pin TQFP (Top View)
CNTENR
CNTENL
ADSR
CLKR
ADSL
CLKL
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
A9R
A10R
A11R
A12R
A13R
A14R
[6]
A15R
[7]
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
GND
R/WR
OER
FT/PIPER
GND
[6]
A14L
[7]
A15L
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
FT/PIPEL
CY7C09289V (64K x 16)
CY7C09279V (32K x 16)
CY7C09269V (16K x 16)
A8R
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
[8]
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
A0L
[8]
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O9R
GND
GND
I/01R
VCC
VCC
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
Notes
6. This pin is NC for CY7C09269V.
7. This pin is NC for CY7C09269V and CY7C09279V.
8. For CY7C09269V and CY7C09279V, pin #18 connected to V
CC
is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin compatible
to an IDT 5V x16 flow through device.
Document #: 38-06056 Rev. *C
I/O0L
NC
Page 2 of 19
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Pinouts
(continued)
Figure 2. 100-Pin TQFP (Top View)
CNTENR
CNTENL
ADSR
CLKR
ADSL
CLKL
GND
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
75
74
73
72
71
70
69
68
67
66
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
A14L
LBL
UBL
CE0L
CE1L
CNTRSTL
R/WL
OEL
VCC
FT/PIPEL
I/O17L
I/O16L
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O11L
I/O10L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
LBR
UBR
CE0R
CE1R
CNTRSTR
R/WR
GND
OER
FT/PIPER
I/O17R
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
[9]
[10]
A15L
[9]
[10]
CY7C09389V (64K x 18)
CY7C09379V (32K x 18)
CY7C09369V (16K x 18)
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O9R
I/01R
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
Selection Guide
Specifications
f
MAX2
(MHz) (Pipelined)
Max. Access Time (ns)
(Clock to Data, Pipelined)
Typical Operating Current
I
CC
(mA)
Typical Standby Current for
I
SB1
(mA)
(Both Ports TTL Level)
Typical Standby Current for
I
SB3
(μA)
(Both Ports CMOS Level)
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-6
[1, 2]
100
6.5
175
25
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-7
[2]
83
7.5
155
25
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-9
67
9
135
20
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-12
50
12
115
20
10
I/O0L
10
10
I/10R
GND
GND
VCC
VCC
10
Notes
9. This pin is NC for CY7C09369V.
10. This pin is NC for CY7C09369V and CY7C09379V.
Document #: 38-06056 Rev. *C
Page 3 of 19
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Pin Definitions
Left Port
A
0L
–A
15L
ADS
L
Right Port
A
0R
–A
15R
ADS
R
Description
Address Inputs
(A
0
–A
14
for 32K, A
0
–A
13
for 16K devices).
Address Strobe Input.
Used as an address qualifier. This signal must be asserted LOW to access
the part using an externally supplied address. Asserting this signal LOW also loads the burst counter
with the address present on the address pins.
Chip Enable Input.
To select either the left or right port, both CE
0
AND CE
1
must be asserted to their
active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Clock Signal.
This input can be free running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input.
Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW.
Counter Reset Input.
Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output
(I/O
0
–I/O
15
for x16 devices).
Lower Byte Select Input.
Asserting this signal LOW enables read and write operations to the lower
byte. (I/O
0
–I/O
8
for x18, I/O
0
–I/O
7
for x16) of the memory array. For read operations both the LB and
OE signals must be asserted to drive output data on the lower byte of the data pins.
Upper Byte Select Input.
Same function as LB, but to the upper byte (I/O
8/9L
–I/O
15/17L
).
Output Enable Input.
This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input.
This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
Flow Through/Pipelined Select Input.
For flow through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle powers down
the internal circuitry to reduce the static power consumption. The
use of multiple Chip Enables enables easier banking of multiple
chips for depth expansion configurations. In the pipelined mode,
one cycle is required with CE
0
LOW and CE
1
HIGH to reactivate
the outputs.
Counter enable inputs are provided to stall the operation of the
address input and use the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This reads/writes one word from or into
each successive address location, until CNTEN is deasserted.
The counter can address the entire memory array and loop back
to the start. Counter Reset (CNTRST) is used to reset the burst
counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
CE
0L
, CE
1L
CLK
L
CNTEN
L
CNTRST
L
CE
0R
,CE
1R
CLK
R
CNTEN
R
CNTRST
R
I/O
0L
–I/O
17L
I/O
0R
–I/O
17R
LB
L
LB
R
UB
L
OE
L
R/W
L
FT/PIPE
L
GND
NC
V
CC
UB
R
OE
R
R/W
R
FT/PIPE
R
Functional Description
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are
high speed 3.3V synchronous CMOS 16K, 32K, and 64K x 16/18
dual-port static RAMs. Two ports are provided, permitting
independent, simultaneous access for reads and writes to any
location in memory
[11]
. Registers on control, address, and data
lines allow for minimal setup and hold times. In pipelined output
mode, data is registered for decreased cycle time. Clock to data
valid t
CD2
= 6.5 ns
[1, 2]
(pipelined). Flow through mode can also
be used to bypass the pipelined output register to eliminate
access latency. In flow through mode, data is available t
CD1
=
18 ns after the address is clocked into the device. Pipelined
output or flow through mode is selected through the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the LOW to HIGH
transition of the clock signal. The internal write pulse is self timed
to allow the shortest possible cycle times.
Note
11. When writing simultaneously to the same location, the final value cannot be guaranteed.
Document #: 38-06056 Rev. *C
Page 4 of 19
[+] Feedback
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
