Data Sheet
PT7A4401C T1/E1 System Synchronizer
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Features
• Meets jitter requirements for AT&T TR62411
Stratum 4 and Stratum 4 Enhanced for DS1
interfaces, and for ETSI ETS300 011 for E1 inter-
faces
• Provides C1.5, C3, C2, C4, C8 and C16 output
clock signals
• Provides 3 kinds of 8kHz framing signals
• Selectable 1.544MHz, 2.084MHz or 8kHz input
reference signals
• Operates in either Normal or Free-Run states
• Enhanced in jitter and duty cycle comparing with
PT7A4401B
• Package: 28-pin PLCC (PT7A4401CJ)
Introduction
PT7A4401C is functionally enhanced version of
PT7A4401B. It has better jitter performance and C16
whose output duty cycle is independent of 20MHz
master clock.
The PT7A4401C employs a digital phase-locked loop
(DPLL) to provide timing and synchronizing signals
for multitrunk T1 and E1 primary rate transmission
links. It generates the ST-BUS clock and framing sig-
nals that are phase-locked to input reference signals
of either 2.048MHz, 1.544MHz or 8kHz.
The PT7A4401C is compliant with AT&T TR62411
Stratum 4 and Stratum 4 Enhanced, and ETSI ETS
300 011. It meets the requirements for jitter tolerance,
jitter transfer, intrinsic jitter, frequency accuracy, cap-
ture range and phase slope, etc.
Applications
• Synchronization and timing control for multitrunk
T1 and E1 systems
• ST-BUS clock and frame pulse sources
PT0108(09/02)
1
Ver:0
Data Sheet
PT7A4401C T1/E1 System Synchronizer
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Contents
Contents
Page
Features ............................................................................................................................................... 1
Applications ........................................................................................................................................ 1
Introduction ......................................................................................................................................... 1
Block Diagram .................................................................................................................................... 3
Pin Information ................................................................................................................................... 4
Pin Assignment .......................................................................................................................... 4
Pin Configuration ...................................................................................................................... 4
Pin Description .......................................................................................................................... 5
Functional Description ........................................................................................................................ 6
Overall Operation ...................................................................................................................... 6
States of Operation .................................................................................................................... 7
Applications Information ........................................................................................................... 8
Detailed Specifications ...................................................................................................................... 10
Definition of Critical Performance Specifications .................................................................... 10
Absolute Maximum Ratings .................................................................................................... 11
Recommended Operating Conditions ...................................................................................... 11
DC Electrical and Power Supply Characteristics ..................................................................... 12
AC Electrical Characteristics ................................................................................................... 13
Mechanical Specifications ....................................................................................................... 25
Ordering Information ........................................................................................................................ 26
Notes ................................................................................................................................................. 27
PT0108(09/02)
2
Ver:0
Data Sheet
PT7A4401C T1/E1 System Synchronizer
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Block Diagram
Figure 1. Block Digram
V
CC
GND
Output Circuit
REF
Phase
Detector
Limiter &
Loop Filter
DCO1
T1
Divider
C1.5
C3
C2
E1
Input
Impairment
Monitor
State
Machine
DCO2
Divider
C4
C8
C16
F0
F8
F16
OSCi
OSCo
Master
Clock
Feedback
Frequency
Select MUX
RST
MS
FS1
FS2
PT0108(09/02)
3
Ver:0
Data Sheet
PT7A4401C T1/E1 System Synchronizer
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pin Information
Pin Assignment
Table 1. Pin Assignment
G r ou p s
Chip Clock
Power & Ground
Clock and Framing Output
Control Signals
Reference Input
Symb ols
OSCi, OSCo
V
CC
, GND
C1.5, C3, C2, C4, C8, C16, F0,
F8, F16
MS, FS1, FS2, RST
REF
F u n ct ion s
Clock
Power
Clock and Framing Signals
Control
Reference Clock
Pin Configuration
Figure 2. Pin Configuration
GND
RST
REF
FS1
4 3
V
CC
OSCo
OSCi
F16
F0
F8
C1.5
5
6
7
8
9
10
11
2 1 28 27 26
25
24
23
28-Pin
PLCC
22
21
20
19
NU
NU
MS
NU
NU
NC
NU
12 13 14 15 16 17 18
GND
C16
V
CC
C3
C2
C4
C8
Top View
PT0108(09/02)
FS2
NU
NU
4
Ver:0
Data Sheet
PT7A4401C T1/E1 System Synchronizer
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pin Description
Table 2. Pin Description
P in
1, 15
2, 3, 19, 21,
22, 24, 25
4
5, 18
6
7
Na m e
GND
NU
REF
V
cc
OSCo
OSCi
Typ e
Ground
I
I
Power
O
I
G r ou n d (0V)
Descr ip t ion
Not Used (should be connected to ground)
R efer en ce I n p u t (T T L com p a t ib le): Input reference signals
Power Su p p ly (+5V)
O scilla t or Ma st er C lock O u t p u t (C MO S): Output of 20MHz master clock
O scilla t or M a st er C lock I n p u t (C M O S): Input of 20MHz master clock (can be
connected directly to a clock source)
F r a m e P u lse O u t p u t (C MO S C om p a t ib le): 8kHz framing output pulse that indicates
the start of the ST-BUS frame. The pulse width is based upon the period of the
16.384MHz synchronization clock.
F r a m e P u lse O u t p u t (C MO S C om p a t ib le): 8kHz output framing pulse that indicates
the start of the active ST-BUS frame. The pulse width is based upon the period of the
4.096MHz synchronization clock.
F r a m e P u lse O u t p u t (C MO S C om p a t ib le): 8kHz output framing pulse that indicates
the start of the active ST-BUS frame. The pulse width is based upon the period of the
8.192MHz synchronization clock.
1.544MH z C lock (C MO S C om p a t ib le)
3.088MH z C lock (C MO S C om p a t ib le)
2.048MH z C lock (C MO S C om p a t ib le)
4.096MH z C lock (C MO S C om p a t ib le)
8.192MH z C lock (C MO S C om p a t ib le)
16.384MH z C lock (C MO S C om p a t ib le)
Not C on n ect ed : Make no connection to this pin.
Mod e Select (T T L C om p a t ib le): This input selects the operation mode of the device,
i.e., Normal or Freerun. Refer to Table 4.
F r eq u en cy Select 2 (T T L C om p a t ib le): This input, together with FS1, selects the
frequency of the input reference signal, either 8kHz, 1.544MHz or 2.048MHz. Refer to
Table 3.
F r eq u en cy Select 1 (T T L C om p a t ib le): Refer to the pin description of FS2.
R eset (C MO S I n p u t Sch m it t Tr igger ): Reset the device when at low level. The reset
is needed when power-up or when frequency select input change to ensure proper
operation. The time constant for a power-up reset circuit must be a min. of five times the
rise time of the power supply. In normal operation, the RST pin must be held low for a
min. of 300 ns to reset the device. When RST at low level, all outputs are fixed at HIGH.
8
F16
O
9
F0
O
10
F8
O
11
12
13
14
16
17
20
23
C1.5
C3
C2
C4
C8
C16
NC
MS
O
O
O
O
O
O
O
I
26
27
FS2
FS1
I
I
28
RST
I
PT0108(09/02)
5
Ver:0
瑞萨MCU/MPU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
