M-8870
DTMF Receiver
Features
•
•
•
•
•
•
•
Low Power Consumption
Adjustable Acquisition and Release Times
Central Office Quality and Performance
Power-down and Inhibit Modes (-02 only)
Inexpensive 3.58 MHz Time Base
Single 5 Volt Power Supply
Dial Tone Suppression
Description
The M-8870 is a full DTMF Receiver that integrates
both bandsplit filter and decoder functions into a single
18-pin DIP or SOIC package. Manufactured using
CMOS process technology, the M-8870 offers low
power consumption (35 mW max) and precise data
handling. Its filter section uses switched capacitor
technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting
techniques to detect and decode all 16 DTMF tone
pairs into a 4-bit code. External component count is
minimized by provision of an on-chip differential input
amplifier, clock generator, and latched tri-state inter-
face bus. Minimal external components required
include a low-cost 3.579545 MHz color burst crystal, a
timing resistor, and a timing capacitor.
The M-8870-02 provides a “power-down” option
which, when enabled, drops consumption to less
than 0.5 mW. The M-8870-02 can also inhibit the
decoding of fourth column digits (see Tone Decoding
table on page 5).
Ordering Information
Part #
M-8870-01
M-8870-01SM
M-8870-01SMTR
M-8870-02
M-8870-02SM
M-8870-02T
Block Diagram
Description
18-pin plastic DIP
18-pin plastic SOIC
18-pin plastic SOIC, tape and reel
18-pin plastic DIP, power-down,
option
18-pin plastic SOIC, power-down,
option
18-pin plastic SOIC, power-down
option, tape and reel
Applications
•
•
•
•
•
Telephone switch equipment
Remote data entry
Paging systems
Personal computers
Credit card systems
Pin Configuration
DS-M8870-R3
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1
M-8870
Absolute Maximum Ratings
Parameter
Power supply voltage (V
DD
- V
SS
)
Voltage on any pin
Current on any pin
Operating temperature
Storage temperature
Symbol
V
DD
V
DC
I
DD
T
A
T
S
Value
6.0 V max
V
SS
-0.3, VDD +0.3
10 mA max
-40°C to + 85°C
-65°C to + 150°C
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an extend-
ed period may degrade the device and effect its reliability.
Note:
Exceeding these ratings may cause permanent damage. Functional operation under
these conditions is not implied.
DC Characteristics
Parameter
Operating supply voltage
Operating supply current
Standby supply current (see Note 3)
Power consumption
Low level input voltage
High level input voltage
Input leakage current
Pullup (source) current on OE
Input impedance, signal inputs 1, 2
Steering threshold voltage
Low level output voltage
High level output voltage
Output low (sink) current
Output high (source) current
Output voltage V
REF
Output resistance V
REF
Symbol
V
DD
I
DD
I
DD
Q
P
O
V
IL
V
IH
I
IH
/I
IL
I
SO
R
IN
V
TSt
V
OL
V
OH
I
OL
I
OH
V
REF
R
OR
Min
4.75
-
-
-
-
3.5
-
-
8
2.2
-
V
DD
- 0.03
1.0
0.4
2.4
-
Typ
-
3.0
-
15
-
-
0.1
6.5
10
-
-
-
2.5
0.8
-
10
Max
5.25
7.0
100
35
1.5
-
-
15.0
-
2.5
0.03
-
-
-
2.7
-
Units
V
mA
µA
mW
V
V
µA
µA
mΩ
V
V
V
mA
mA
V
kΩ
Test Conditions
-
-
PD=V
DD
f = 3.579 MHz, V
DD
= 5.0 V
-
-
V
IN
= V
SS
or V
DD
(see Note 2)
OE = 0 V
@ 1 kHz
-
No load
No load
V
OUT
= 0.4 V
V
OUT
= V
DD
- 0.4 V
No load
-
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Operating Characteristics - Gain Setting Amplifier
Parameter
Input leakage current
Input resistance
Input offset voltage
Power supply rejection
Common mode rejection
DC open loop voltage gain
Open loop unity gain bandwidth
Output voltage swing
Tolerable capacitive load (GS)
Tolerable resistive load (GS)
Common mode range
Symbol
I
N
R
IN
V
OS
PSRR
CMRR
A
VOL
f
C
V
O
C
L
R
L
V
CM
Min
-
4
-
50
55
60
1.2
3.5
-
-
2.5
Typ
± 100
-
± 25
-
-
-
1.5
-
-
-
-
Max
-
-
-
-
-
-
-
-
100
50
-
Units
nA
MΩ
mV
dB
dB
dB
MHz
V
P-P
pF
kΩ
V
P-P
Test Conditions
V
SS
< V
IN
< V
DD
-
-
1 KHz
-3.0V < V
IN
< 3.0V
-
-
RL
≈
100 KΩ to V
SS
-
-
No load
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Notes:
1. All voltages referenced to V
SS
unless otherwise noted. For typical values, V
DD
= 5.0V, V
SS
= 0V, TA = 25°C.
2
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Rev. 3
M-8870
Steering Circuit
Before a decoded tone pair is registered, the receiver
checks for a valid signal duration (referred to as char-
acter-recognition-condition). This check is performed
by an external RC time constant driven by ESt. A logic
high on ESt causes VC (see block diagram on page 1)
to rise as the capacitor discharges. Provided that sig-
nal condition is maintained (ESt remains high) for the
validation period (t
GTF
), V
C
reaches the threshold (V
TSt
)
of the steering logic to register the tone pair, thus latch-
ing its corresponding 4-bit code (see DC
Characteristics on page 2) into the output latch. At this
point, the GT output is activated and drives V
C
to V
DD
.
GT continues to drive high as long as ESt remains
high. Finally, after a short delay to allow the output
latch to settle, the delayed steering output flag (StD)
goes high, signaling that a received tone pair has been
registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three-
state control input (OE) to a logic high. The steering
circuit works in reverse to validate the interdigit pause
between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate
signal interruptions (dropouts) too short to be consid-
ered a valid pause. This capability, together with the
ability to select the steering time constants externally,
allows the designer to tailor performance to meet a
wide variety of system requirements.
Single-Ended Input Configuration
Functional Description
M-8870 operating functions (see block diagram on
page 1) include a bandsplit filter that separates the
high and low tones of the received pair, and a digital
decoder that verifies both the frequency and duration
of the received tones before passing the resulting 4-bit
code to the output bus.
Filter
The low and high group tones are separated by apply-
ing the dual-tone signal to the inputs of two 6th order
switched capacitor bandpass filters with bandwidths
that correspond to the bands enclosing the low and
high group tones. The filter also incorporates notches
at 350 and 440 Hz, providing excellent dial tone rejec-
tion. Each filter output is followed by a single-order
switched capacitor section that smooths the signals
prior to limiting. Signal limiting is performed by high-
gain comparators provided with hysteresis to prevent
detection of unwanted low-level signals and noise.
The comparator outputs provide full-rail logic swings
at the frequencies of the incoming tones.
Decoder
The M-8870 decoder uses a digital counting tech-
nique to determine the frequencies of the limited tones
and to verify that they correspond to standard DTMF
frequencies. A complex averaging algorithm is used to
protect against tone simulation by extraneous signals
(such as voice) while tolerating small frequency varia-
tions. The algorithm ensures an optimum combination
of immunity to talkoff and tolerance to interfering sig-
nals (third tones) and noise. When the detector rec-
ognizes the simultaneous presence of two valid tones
(known as signal condition), it raises the Early
Steering flag (ESt). Any subsequent loss of signal
condition will cause ESt to fall.
Basic Steering Circuit
Rev. 3
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3
M-8870
Pin Functions
Pin
Name
1
IN+
2
IN-
3
GS
4
V
REF
5
INH*
6
PD*
7
OSC1
8
OSC2
9
VSS
10
OE
11-14 Q1, Q2,
Q3, Q4
15
StD
16
17
ESt
St/GT
Non-inverting input
Inverting input
Gain select. Gives access to output of front-end amplifier for connection of feedback resistor.
Reference voltage output (nominally VDD/2). May be used to bias the inputs at mid-rail.
Inhibits detection of tones representing keys A, B, C, and D.
Power down. Logic high powers down the device and inhibits the oscillator. Internal pulldown.
Clock input
3.579545 MHz crystal connected between these pins completes the internal oscillator.
Clock output
Negative power supply (normally connected to 0 V).
Tri-statable output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup.
Tri-statable data outputs. When enabled by OE, provides the code corresponding to the last valid tone pair
received (see Tone Decoding table on page 5).
Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is
updated. Returns to logic low when the voltage on St/GT falls below VTSt.
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (signal
condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the
detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT
output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St. (See
Common Crystal Connection on page 5).
Positive power supply. (Normally connected to +5V.)
Description
Connections to the front-end differential amplifier.
18
V
DD
* -02 only. Connect to V
SS
for -01 version
Guard Time Adjustment
Where independent selection of signal duration and
interdigit pause are not required, the simple steering
circuit of Basic Steering Circuit is applicable.
Component values are chosen according to the formu-
la:
t
REC
= t
DP
+ t
GTP
t
GTP
@ 0.67 RC
registered. On the other hand, a relatively short t
REC
with a long t
DO
would be appropriate for extremely
noisy environments where fast acquisition time and
immunity to dropouts would be required. Design infor-
mation for guard time adjustment is shown in the
Guard Time Adjustment below.
Power-down and Inhibit Mode (-02 only)
A logic high applied to pin 6 (PD) will place the device
into standby mode to minimize power consumption. It
Figure 5 Guard Time Adjustment
The value of tDP is a parameter of the device and
tREC is the minimum signal duration to be recognized
by the receiver. A value for C of 0.1 µF is recommend-
ed for most applications, leaving R to be selected by
the designer. For example, a suitable value of R for a
t
REC
of 40 ms would be 300 kΩ. A typical circuit using
this steering configuration is shown in the Single -
Ended Input Configuration on page 4. The timing
requirements for most telecommunication applications
are satisfied with this circuit. Different steering arrange-
ments may be used to select independently the guard
times for tone-present (t
GTP
) and tone-absent (t
GTA
).
This may be necessary to meet system specifications
that place both accept and reject limits on both tone
duration and interdigit pause.
Guard time adjustment also allows the designer to tai-
lor system parameters such as talkoff and noise immu-
nity. Increasing t
REC
improves talkoff performance,
since it reduces the probability that tones simulated by
speech will maintain signal condition long enough to be
4
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Rev. 3
M-8870
stops the oscillator and the functioning of the filters.
On the M-8870-01 models, this pin is tied to ground
(logic low).
Inhibit mode is enabled by a logic high input to pin 5
(INH). It inhibits the detection of 1633 Hz. The output
code will remain the same as the previous detected
code (see Pin functions table on page 4). On the M-
8870-01 models, this pin is tied to ground (logic low).
Input Configuration
The input arrangement of the M-8870 provides a dif-
ferential input operational amplifier as well as a bias
source (V
REF
) to bias the inputs at mid-rail. Provision
is made for connection of a feedback resistor to the
op-amp output (GS) for gain adjustment.
Tone Decoding
FLOW
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
ANY
FHIGH
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
ANY
Key (ref.)
1
2
3
4
5
6
7
8
9
0
S
#
A
B
C
D
ANY
OE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Q4
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Z
Q3
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Z
Q2
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Z
Q1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Z
In a single-ended configuration, the input pins are
connected as shown in the Single - Ended Input
Configuration on page 3 with the op-amp connected
for unity gain and V
REF
biasing the input at 1/2V
DD
.
The Differential Input Configuration bellow permits
gain adjustment with the feedback resistor R
5
.
DTMF Clock Circuit
The internal clock circuit is completed with the addition
of a standard 3.579545 MHz television color burst crys-
tal. The crystal can be connected to a single M-8870 as
shown in the Single - Ended Input Configuration on
page 3, or to a series of M-8870s. As illustrated in the
Common Crystal Connection below, a single crystal
can be used to connect a series of M-8870s by cou-
pling the oscillator output of each M-8870 through a 30
pF capacitor to the oscillator input of the next M-8870.
L = logic low, H = logic high, Z = high impedance
Differential Input Configuration
Common Crystal Connection
Rev. 3
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