M-8880
DTMF Transceiver
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Advanced CMOS technology for low power consump-
tion and increased noise immunity
Complete DTMF transmitter/receiver in a single chip
Standard 6500/6800 series microprocessor port
Central office quality and performance
Adjustable guard time
Automatic tone burst mode
Call progress mode
Single +5 Volt power supply
20-pin DIP and SOIC packages
2 MHz microprocessor port operation
Inexpensive 3.58 MHz crystal
No continuous
f2
clock required, only strobe
Applications include: paging systems, repeater sys-
tems/mobile radio, interconnect dialers, PBX systems,
computer systems, fax machines, pay telephones,
credit card verification
Figure 1 Pin Diagram
Functional Description
M-8880 functions consist of a high-performance DTMF receiver
with an internal gain setting amplifier and a DTMF generator that
contains a tone burst counter for generating precise tone bursts
and pauses. The call progress mode, when selected, allows the
detection of call progress tones. A standard 6500/6800 series
microprocessor interface allows access to an internal status
register, two control registers, and two data registers.
Input Configuration
The input arrangement consists of a differential input opera-
tional amplifier and bias sources (V
REF
) for biasing the amplifier
inputs at V
DD
/2. Provisions are made for the connection of a
feedback resistor to the op-amp output (GS) for gain adjust-
The M-8880 is a complete DTMF Transmitter/Receiver that fea-
tures adjustable guard time, automatic tone burst mode, call
progress mode, and a fully compatible 6500/6800 microproces-
sor interface. The receiver portion is based on the industry stan-
dard M-8870 DTMF Receiver, while the transmitter uses a
switched-capacitor digital-to-analog converter for
low-distortion, highly accurate DTMF signaling. Tone bursts can
be transmitted with precise timing by making use of the auto-
matic tone burst mode. To analyze call progress tones, a call
progress filter can be selected by an external microprocessor.
Figure 2 Block Diagram
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M-8880
Figure 3 Single-Ended Input Configuration
Figure 4 Differential Input Configuration
ment. In a single-ended configuration, the input pins should be
connected as shown in Figure 3. Figure 4 shows the necessary
connections for a differential input configuration.
Receiver Section
The low and high group tones are separated by applying the
DTMF signal to the inputs of two sixth-order switched capacitor
bandpass filters with bandwidths that correspond to the low and
high group frequencies listed in Table 2. The low group filter in-
corporates notches at 350 and 440 Hz, providing excellent dial
tone rejection. Each filter output is followed by a single-order
switched capacitor filter that smooths the signals prior to limiting.
Limiting is performed by high-gain comparators with hysteresis
to prevent detection of unwanted low-level signals. The com-
parator outputs provide full-rail logic swings at the incoming
DTMF signal frequencies.
A decoder employs digital counting techniques to determine the
frequencies of the incoming tones, and to verify that they corre-
spond to standard DTMF frequencies. A complex averaging al-
gorithm protects against tone simulation by extraneous signals
(such as voice), while tolerating small deviations in frequency.
The algorithm provides an optimum combination of immunity to
talkoff with tolerance to interfering frequencies (third tones) and
noise. When the detector recognizes the presence of two valid
tones (referred to as “signal condition”), the early steering (ESt)
output goes to an active state. Any subsequent loss of signal
condition will cause ESt to assume an inactive state.
Steering Circuit:
Before a decoded tone pair is registered, the
receiver checks for a valid signal duration (referred to as “char-
acter recognition condition”). This check is performed by an ex-
ternal RC time constant driven by ESt. A logic high on ESt
Table 1 Pin Functions
Name
IN+
IN-
GS
V
REF
V
SS
OSC1
OSC2
TONE
R/W
CS
RS0
φ2
IRQ/CP
Description
Noninverting op-amp input.
Inverting op-amp input.
Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor.
Reference voltage output. Nominally V
DD
/2 is used to bias inputs at mid-rail.
Negative power supply input.
DTMF clock/oscillator input.
Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit.
Dual tone multifrequency (DTMF) output.
Read/write input. Controls the direction of data transfer to and from the microprocessor and the receiver/transmitter. TTL
compatible.
Chip select. TTL input (CS = 0 to select the chip).
Register select input. See Table 6. TTL compatible.
System clock input. May be continuous or strobed only during read or write. TTL compatible.
Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and inter-
rupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Figure 11
Microprocessor data bus. TTL compatible.
Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any
momentary loss of signal condition will cause ESt to return to a logic low.
Steering input/guard time output (bidirectional). A voltage greater than V
TSt
detected at St causes the device to register the
detected tone pair and update the output latch. A voltage less than V
TSt
frees the device to accept a new tone pair. The
GT output acts to reset the external steering time-constant; its state is a funciton of ESt and the voltage on St.
Positive power supply input.
D0 - D3
ESt
St/GT
V
DD
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M-8880
causes V
C
(see Figure 5) to rise as the capacitor discharges.
Provided that the signal condition is maintained (ESt remains
high) for the validation period (t
GTP
), V
C
reaches the threshold
(V
TSt
) of the steering logic to register the tone pair, latching its
corresponding 4-bit code (see Table 2) into the receive data reg-
ister.
Table 2 Tone Encoding/Decoding
F
LOW
697
697
697
770
770
770
852
852
852
941
941
F
HIGH
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
Digit
1
2
3
4
5
6
7
8
9
0
D3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
D1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
The steering circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate signal in-
terruptions (dropout) too short to be considered a valid pause.
This capability, together with the ability to select the steering
time constants externally, allows the designer to tailor perfor-
mance to meet a wide variety of system requirements.
Guard Time Adjustment:
The simple steering circuit shown in
Figure 5 is adequate for most applications. Component values
are chosen according to the formula:
t
REC
= t
DP
+ t
GTP
T
ID
= t
DA
+ t
GTA
The value of t
DP
is a device parameter and t
REC
is the minimum
signal duration to be recognized by the receiver. A value for C1
of 0.1
µF
is recommended for most applications, leaving R1 to
be selected by the designer. Different steering arrangements
may be used to select independently the guard times for tone
present (t
GTP
) and tone absent (t
GTA
). This may be necessary to
meet system specifications that place both accept and reject
limits on both tone duration and interdigit pause. Guard time ad-
justment also allows the designer to tailor system parameters
such as talkoff and noise immunity. Increasing t
REC
improves
talkoff performance since it reduces the probability that tones
simulated by speech will maintain signal condition long enough
to be registered. Alternatively, a relatively short t
REC
with a long
t
DO
would be appropriate for extremely noisy environments
where fast acquisition time and immunity to tone dropouts are
required. Design information for guard time adjustment is shown
in Figure 6.
*
941
1477
#
697
1633
A
770
1633
B
852
1633
C
941
1633
D
0 = logic low, 1 = logic high
At this point the StGT output is activated and drives V
C
to V
DD
.
StGT continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to settle, the
delayed steering output flag goes high, signaling that a received
tone pair has been registered. It is possible to monitor the status
of the delayed steering flag by checking the appropriate bit in the
status register. If interrupt mode has been selected, the IRQ/CP
pin will pull low when the delayed steering flag is active.
Figure 6 Guard Time Adjustment
Figure 5 Basic Steering Circuit
Call Progress Filter
A call progress (CP) mode can be selected, allowing the detec-
tion of various tones that identify the progress of a telephone call
on the network. The call progress tone input and DTMF input are
common; however, call progress tones can only be detected
when the CP mode has been selected. DTMF signals cannot be
The contents of the output latch are updated on an active de-
layed steering transition. This data is presented to the 4-bit
bidirectional data bus when the receive data register is read.
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M-8880
detected if the CP mode has been selected (see Table 3). Fig-
ure 7 indicates the useful detect bandwidth of the call progress
filter. Frequencies presented to the input (IN+ and IN-) that are
within the “accept” bandwidth limits of the filter are hard-limited
by a high-gain comparator with the IRQ /CP pin serving as the
output. The square wave output obtained from the schmitt trig-
ger can be analyzed by a microprocessor or counter arrange-
ment to determine the nature of the call progress tone being
detected. Frequencies in the “reject” area will not be detected,
and consequently there will be no activity on IRQ /CP as a result
of these frequencies.
accuracy. When there is no tone output signal, the TONE pin
assumes a DC level of 2.5 volts (typically). A bandwidth limiting
filter is incorporated to attenuate distortion products above 4
KHz.
Burst Mode:
Certain telephony applications require that gener-
ated DTMF signals be of a specific duration, determined either
by the application or by any of the existing exchange transmitter
specifications. Standard DTMF signal timing can be accom-
plished by making use of the burst mode. The transmitter is ca-
pable of issuing symmetric bursts/pauses of predetermined
duration. This burst/pause duration is 51 ms
±
1 ms, a standard
interval for autodialer and central office applications. After the
burst/pause has been issued, the appropriate bit is set in the sta-
tus register, indicating that the transmitter is ready for more data.
The timing described is available when the DTMF mode has
been selected. However, when call progress (CP) mode is se-
lected, a secondary burst/pause time is available that extends
this interval to 102 ms
±
2 ms. The extended interval is useful
when precise tone bursts of longer than 51 ms duration and 51
ms pause are desired. Note that when CP mode and burst mode
have been selected, DTMF tones may be transmitted only and
not
received. In applications requiring a nonstandard
burst/pause time, use a software timing loop or external timer.
This provides the timing pulses when the burst mode is disabled
by enabling and disabling the transmitter.
Figure 7 Call Progress Response
DTMF Generator
The DTMF transmitter used in the M-8880 is capable of generat-
ing all 16 standard DTMF tone pairs with low distortion and high
accuracy. All frequencies are derived from an external 3.58
MHz crystal. The sinusoidal waveforms for the individual tones
are digitally synthesized using row and column programmable
dividers and switched capacitor digital-to-analog converters.
The row and column tones are mixed and filtered, providing a
DTMF signal with low total harmonic distortion and high accu-
racy. To specify a DTMF signal, data conforming to the encod-
ing format shown in Table 2 must be written to the transmit data
register. Note that this is the same as the receiver output code.
The individual tones that are generated (f
LOW
and f
HIGH
) are re-
ferred to as low-group and high-group tones. Typically, the
high-group to low-group amplitude ratio (twist) is 2 dB to com-
pensate for high-group attenuation on long loops.
Operation:
During write operations to the transmit data register,
4-bit data on the bus is latched and converted to a 2 of 8 code for
use by the programmable divider circuitry to specify a time seg-
ment length that will ultimately determine the tone frequency.
The number of time segments is fixed at 32, but the frequency is
varied by varying the segment length. When the divider reaches
the appropriate count as determined by the input code, a reset
pulse is issued and the counter starts again. The divider output
clocks another counter that addresses the sinewave lookup
ROM. The lookup table contains codes used by the switched
capacitor D/A converter to obtain discrete and highly accurate
DC voltage levels. Two identical circuits are used to produce
row and column tones, which are then mixed using a low-noise
summing amplifier. The oscillator described needs no “startup”
time as in other DTMF generators, since the crystal oscillator is
running continuously, thus providing a high degree of tone burst
The M-8880 is initialized on powerup sequence with DTMF
mode and burst mode selected.
Single-Tone Generation:
A single-tone mode is available
whereby individual tones from the low group or high group can
be generated. This mode can be used for DTMF test equipment
applications, acknowledgment tone generation, and distortion
measurements. Refer to Table 4 for details.
Distortion Calculations:
The M-8880 is capable of producing
precise tone bursts with minimal error in frequency (see Table
3). The internal summing amplifier is followed by a first-order
low-pass switched capacitor filter to minimize harmonic compo-
nents and intermodulation products. The total harmonic distor-
tion for a
single
tone can be calculated using Equation 1, (see
Figure 9) which is the ratio of the total power of all the extrane-
ous frequencies to the power of the fundamental frequency ex-
pressed as a percentage. The Fourier components of the tone
output correspond to V2f... Vnf as measured on the output
waveform. The total harmonic distortion for a
dual
tone can be
calculated using Equation 2 (see Figure 9).
Table 3 Actual Frequencies vs. Standard
Requirements
Active
Cell
L1
L2
L3
L4
H1
H2
H3
H4
Output Frequency (Hz)
Specified
Actual
697
770
852
941
1209
1336
1447
1633
699.1
766.2
847.4
948.0
1215.9
1331.7
1471.9
1645.0
% Error
+ 0.30
- 0.49
- 0.54
+ 0.74
+ 0.57
- 0.32
- 0.35
+ 0.73
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M-8880
Table 4 Control Register A Description
Bit
b0
b1
Name
TOUT
CP/DTMF
Function
Tone output
Description
b2
IRQ
b3
RSET
A logic 1 enables the tone output. This function can be implemented in either the burst mode or
nonburst mode.
Mode control In DTMF mode (logic 0), the device is capable of generating and receiving DTMF signals. When
the call progress (CP) mode is selected (logic 1), a 6th-order bandpass filter is enabled to allow
call progress tones to be detected. Call progress tones within the specified bandwidth will be pre-
sented at the IRQ/CP pin in rectangular wave format if the IRQ bit has been enabled (b2 =1). Also,
when the CP mode and burst mode have both been selected, the transmitter will issue DTMF sig-
nals with a burst and pause of 102 ms (typ) duration. This signal duration is twice that obtained
from the DTMF transmitter, if DTMF mode had been selected. Note that DTMF signals cannot be
decoded when the CP mode has been selected.
Interrupt enable A logic 1 enables the interrupt mode. When this mode is active and the DTMF mode has been se-
lected (b1 = 0), the IRQ/CP pin will pull to a logic 0 condition when either (1) a valid DTMF signal
has been received and has been present for the guard time or (2) the transmitter is ready for more
data (burst mode only).
Register select A logic 1 selects control register B on the next write cycle to the control register address. Subse-
quent write cycles to the control register are directed back to control register A.
Table 5 Control Register B Description
Bit
b0
Name
BURST
Function
Burst mode
Description
b1
TEST
b2
S/D
b3
C/R
A logic 0 enables the burst mode. When this mode is selected, data corresponding to the desired
DTMF tone pair can be written to the transmit data register, resulting in a tone burst of a specific
duration (see Table 12). Subsequently, a pause of the same duration is induced. Immediately fol-
lowing the pause, the status register is updated indicating that the transmit data register is ready
for further instructions, and an interrupt will be generated if the interrupt mode has been enabled.
Additionally, if call progress (CP) mode has been enabled, the burst and pause duration is increed
by a factor of two. When the burst mode is not selected (logic 1), tone bursts of any desired dura-
tion may be generated.
Test mode
By enabling the test mode (logic 1), the IRQ/CP pin will present the delayed steering (inverted)
signal from the DTMF receiver. Refer to Figure 11 (b3 waveform) for details concerning the output
waveform. DTMF mode must be selected (CRA b1 = 0) before test mode can be implemented.
Single/dual tone A logic 0 will allow DTMF signals to be produced. If single-tone generation is enabled (logic 1), ei-
generation
ther now or column tones (low or high group) can be generated depending on the state of b3 in
control register B.
Column/row
When used in conjunction with b2 (above), the transmitter can be made to generate single-row or
tones
single-column frequencies. A logic0 will select row frequencies and a logic 1 will select column fre-
quencies.
V
L
and V
H
correspond to the low-group and high-group ampli-
tude, respectively, and V
2
IMD
is the sum of all the intermodulation
components. The internal switched capacitor filter following the
D/A converter keeps distortion products down to a very low
level.
DTMF Clock Circuit
The internal clock circuit is completed with the addition of a stan-
dard 3.579545 MHz television color burst crystal. A number of
M-8880 devices can be connected as shown in Figure 8 using
only one crystal.
Microprocessor Interface
The M-8880 uses a microprocessor interface that allows pre-
cise control of transmitter and receiver functions. Five internal
registers are associated with the microprocessor interface,
which can be subdivided into three categories: data transfer,
transceiver control, and transceiver status. Two registers are
associated with data transfer operations. The receive data,
read-only, contains the output code of the last valid DTMF tone
pair to be decoded. The data entered in the transmit data regis-
ter determines which tone pair is to be generated (see Table 2).
Figure 8 Common Crystal Connection
Data can only be written to the transmit data register. Trans-
ceiver control is accomplished with two control registers (CRA
and CRB), occupying the same address space. A write opera-
tion to CRB can be executed by setting the appropriate bit in
CRA. The following write operation to the same address will
then be directed to CRB, and subsequent write cycles will then
be redirected to CRA. Internal reset circuitry clears the control
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