ADVANCED INFORMATION
MX98726
SINGLE CHIP 10/100 FAST ETHERNET
CONTROLLER WITH uP INTERFACE
1.0 Features
• Direct interface to 80188/186 up to 40Mhz.
• Integrated 10/100 TP tranceiver on chip to reduce
overall cost
• Fully comply to IEEE 802.3u spec.
• Best fit in network printer and hub/switch manage-
ment application
• A local DMA channel between on-chip FIFOs and
packet memory
• Shared memory architecture allow host and
MX98726 to use only one single SRAM
• Host DMA can share packet memory with local DMA
with simple hand shake protocol for x188/186 type of
processor
• Support bus size configuration:
- CPU : 8 bits, SRAM: 8 bits
- CPU : 16 bits, SRAM: 8/16 bits
• Flexible packet buffer partition and addressing space
for 32k, 64k up to 512 bytes
• NWAY autonegociation function to automatically set
up network speed and protocol
• 3 loop back modes for system level diagnostics
• Rich on-chip register set to support a wide variety of
network management functions
• Support 64 bits hash table for multicast addressing
• Support software EEPROM interface for easy up-
grade of EEPROM content
• Support 1K bits and 4K bits EEPROM interface
• 5V CMOS in 128 PQFP package for minimum board
size application
1.1 Introduction
MX98726 ( Generic MAC , or GMAC ) is a cost effective
solution as a generic single chip 10/100 Fast Ethernet
controller. It is designed to directly interface 80188, 80186
( host ) without glue logic. Two types of memory sharing
schemes are supported, i.e. interleaved and shared mode
to support a variety of applications. Single chip solution
will help reduce system cost not only on the compo-
nents but also the board size. Full NWAY function with
10/100 tranceiver will ease the field installation, simply
plug the chip in and it will connect itself with the best
protocol available.
The interleaved mode allow uP to access SRAM (
packet/host buffer ) through MX98726's local DMA chan-
nel. This way, no extra SRAM interface logic is needed
on the host side. If high performance is desired, then
shared memory mode is another alternative which allow
host to access SRAM on its own by denying SRAM bus
grant to MX98726 using simple hand shake protocol.
Without SRAM bus grant, MX98726 will float its inter-
face connected to the SRAM, therefore host can utilize
its own memory subsystem to conduct its own SRAM
access.
A intelligent built-in SRAM bus arbitor will manage all
the SRAM access requests from host, on-chip transmit
channel and on-chip receive channel. The throughput
of these network channels and MX98726's DMA burst
length can be easily adjusted by option bits on the chip.
These options can help system developers to "fine tune"
a best cost/performance ratio.
MX98726 is also equipped with fast back-to-back trans-
mit capability which allow software to "fire" as many
transmit packets as needed in a single command. Re-
ceive FIFO also allow back-to-back reception. Optional
EEPROM can be used to stored network network ad-
dress and other information. In case cost is really a con-
cern, most configuration options including network ad-
dress can be programmed through uP.
P/N:PM0555
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
REV. 0.9.8, FEB. 14, 2000
1
MX98726
2.1 Pin Description : ( all internal pull-up resistor is 168K ohm, pull-down is 70k ohm )
PIN#
82
49-54,
56,57
59-62,
66-69
76
70-73
79
78
81
Pin Name
CLKIN
AD[7:0]
AD[15:8]
ALE
A[19:16]
RDB
WRB
INTB
Type
I, TTL
I/O, 4ma
I/O, 4ma
I,TTL
I, TTL
I, TTL
I, TTL
O/D, 4ma
Description
Host Clock Input : 8M to 40 Mhz.
Multiplexed Address/Data Bit [7:0] :
Multiplexed Address/Data Bit [15:8] :
Address Latch Enable : Active high
Host Address Bit [19:16] : Internal pull-down
Host Read Strobe: Active low.
Host Write Strobe : Active low.
Host Interrupt Output : Polarity can be programmed, default is active low.
For active Low interrupt application, external pull-up is reguired. For active
high interrupt application, external pull-down is required.
Host Byte High Enable :
BHEB A0
Function
0
0
Word Transfer
0
1
Upper Byte Transfer
1
0
Lower Byte Transfer
1
1
Lower Byte Transfer
Synchronous Host Ready Output : Active high synchronized to CLKIN to
indicate data is ready to be transferred. Initially low at the beginning of a
host cycle.
Chip Select : Active low, used to enable GMAC to decode host address.
When high, no host cycle is recognized by MAC.
Host Memory/IO cycle indicator : Set for memory access and reset for IO
access. Internal pull-up. Decode of MIO can be disable by DISMIO regis-
ter bit. Default is enabled.
Packet Memory Bus Hold Request : Active high to request Host to "float"
its interface of the packet memory. Host grants the packet buffer bus to
MX98726 by asserting HLDA = 1.
Packet Memory Bus Hold Acknowledge: Packet buffer bus is granted to
MX98726. If HLDA=0 then MX98726 will float its interface on the packet
buffer. Internal pull-up.
Host Program Strobe Enable : Active low to indicate current cycle is a
ROM access and MX98726 will not decode this ROM cycle. PSENB must
high for packet memory access.
Host Reset Input : Active low
75
BHEB
I,TTL
80
SRDY
O, 4ma
47
48
CSB
MIO
I, TTL
I, TTL
45
HOLD
O, 4ma
46
HLDA
I, TTL
77
PSENB
I, TTL
74
RSTB
I,TTL
P/N:PM0555
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
REV. 0.9.8, FEB. 14, 2000
5
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