CAT24C21
1 kb Dual Mode Serial
EEPROM for VESAt
“Plug-and-Play”
Description
The CAT24C21 is a 1 kb Serial CMOS EEPROM internally
organized as 128 words of 8 bits each. The device complies with the
Video Electronics Standard Association’s (VESA™), Display Data
Channel (DDC™) standards for “Plug−and−Play” monitors. The
“transmit−only” mode (DDC1™) is controlled by the VCLK clock
input and the “bi−directional” mode (DDC2™) is controlled by the
SCL clock input, with both modes sharing a common SDA
input/output (I/O). The transmit−only mode is a read−only mode,
while the bi−directional mode is a read and write mode following the
I
2
C protocol. In write mode the CAT24C21 features a 16−byte page
write buffer. The device is available in 8−lead DIP, SOIC, TSSOP,
MSOP and TDFN packages.
Features
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SOIC−8
W SUFFIX
CASE 751BD
TDFN−8
ZD4 SUFFIX
CASE 511AL
MSOP−8
Z SUFFIX
CASE 846AD
•
•
•
•
•
•
•
•
•
•
•
DDC1t/DDC2t Interface Compliant for Monitor Identification
400 kHz I
2
C Bus Compatible
2.5 to 5.5 Volt Operation
16−byte Page Write Buffer
Hardware Write Protect
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
8−lead DIP, SOIC, TSSOP, MSOP or TDFN Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V
CC
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
NC
NC
NC
V
SS
1
V
CC
VCLK
SCL
SDA
PDIP (L), SOIC (W), TSSOP (Y),
TDFN (ZD4), MSOP (Z)
PIN FUNCTION
Pin Name
NC
Function
No Connect
Serial Data / Address
Serial Clock (bi−directional mode)
Serial Clock (transmit−only mode)
Power Supply
Ground
SCL
CAT24C21
VCLK
SDA
SDA
SCL
VCLK
V
CC
V
SS
V
SS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
Figure 1. Functional Symbol
©
Semiconductor Components Industries, LLC, 2009
September, 2009
−
Rev. 16
1
Publication Order Number:
CAT24C21/D
CAT24C21
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 2)
Ratings
–55 to +125
–65 to +150
–2.0 to +V
CC
+2.0
–2.0 to +7.0
1.0
300
100
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
N
END
(Notes 3 and 4)
T
DR
(Note 3)
V
ZAP
(Note 3)
I
LTH
(Notes 3 and 5)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch−up
Reference Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Units
Program/Erase Cycles
Years
Volts
mA
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Page Mode, V
CC
= 5 V, 25°C
5. Latch−up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+1 V.
Table 3. D.C. OPERATING CHARACTERISTICS
(V
CC
= 2.5 V to 5.5 V, unless otherwise specified. Industrial temperature range.)
Symbol
I
CC
I
SB
(Note 6)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
IL
V
IH
Parameter
Power Supply Current
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Input Low Voltage (VCLK)
Input High Voltage (VCLK)
V
CC
= 3.0 V, I
OL
= 3 mA
V
CC
≥
2.7 V
2.0
Test Conditions
f
SCL
= 400 kHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
−1
V
CC
x 0.7
Min
Max
2
1
10
10
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.8
Units
mA
mA
mA
mA
V
V
V
V
V
6. Maximum standby current (I
SB
) = 10
mA
for the Extended Automotive temperature range.
Table 4. CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V)
Symbol
C
I/O
(Note 7)
C
IN
(Note 7)
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (VCLK, SCL)
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Min
Max
8
6
Units
pF
pF
7. This parameter is tested initially and after a design or process change that affects the parameter.
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CAT24C21
Table 5. A.C. CHARACTERISTICS
(V
CC
= 2.5 V to 5.5 V, unless otherwise specified. Industrial temperature range.)
Symbol
TRANSMIT−ONLY MODE
T
VAA
T
VHIGH
T
VLOW
T
VHZ
T
VPU
F
SCL
T
I
(Note 8)
t
AA
t
BUF
(Note 8)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 8)
t
F
(Note 8)
t
SU:STO
t
DH
t
PUR
t
PUW
t
WR
Output valid from VCLK
VCLK high
VCLK low
Mode transition
Transmit−only power−up
0
0.6
1.3
0.5
0.5
ms
ms
ms
ms
ns
Parameter
Min
Max
Units
READ & WRITE CYCLE LIMITS
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.6
100
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
400
100
1
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
POWER−UP TIMING
(Note 8 and 9)
Power−up to Read Operation
Power−up to Write Operation
1
1
ms
ms
WRITE CYCLE LIMITS
Write Cycle Time
5
ms
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop condition
of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are
disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
Pin Description
Functional Description
The SCL serial clock input pin is used to clock all data
transfers into or out of the device when in the bi−directional
mode.
The SDA bi−directional serial data/address pin is used to
transfer data into and out of the device. The SDA pin is an
open drain output and can be wire−ORed with other open
drain or open collector outputs.
The CAT24C21 has two modes of operation: the
transmit−only mode and the bi−directional mode. There is a
separate 2−wire protocol to support each mode, each having
a separate clock input (VCLK and SCL respectively) and
both modes sharing a common bi−directional data line
(SDA). The CAT24C21 enters the transmit−only mode upon
power up and begins outputting data on the SDA pin with
each clock signal on the VCLK pin. The device will remain
in the transmit−only mode until there is a valid HIGH to
LOW transition on the SCL pin, when it will switch to the
bi−directional mode (Figure 2). Once in the bi−directional
mode, the only way to return to the transmit−only mode is
by powering down the device.
The VCLK serial clock input pin is used to clock data out
of the device when in transmit−only mode. When held low,
in bi−directional mode, it will inhibit write operations.
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CAT24C21
Transmit−Only Mode: (DDC1)
Upon power−up, the CAT24C21 will output valid data
only after it has been initialized. During initialization, data
will not be available until after the first nine clocks are sent
to the device (Figure 3). The starting address for the
transmit−only mode can be determined during initialization.
If the SDA pin is high during the first eight clocks, the
starting address will be 7FH. If the SDA pin is low during the
first eight clocks, the starting address will be 00H. During
the ninth clock, SDA will be in the high impedance state.
Data is transmitted in 8 bit words with the most significant
bit first, followed by a 9th ‘don’t care’ bit which will be in
the high impedance state (Figure 4). The CAT24C21 will
continuously sequence through the entire memory array as
long as VCLK is present and no falling edges on SCL are
detected. When the maximum address (7FH) is reached,
addressing will wrap around to the zero location (00H) and
transmitting will continue. The bi−directional mode clock
(SCL) pin must be held high for the device to remain in the
transmit−only mode.
Transmit−Only Mode
SCL
T
VHZ
SDA
Bi−Directional Mode
VCLK
Figure 2. Mode Transition
SCL
SDA
SDA at high impedance for 9 clock cycles
Bit8
Bit7
Bit6
Bit5
Bit4
VCLK
1
T
VPU
2
3
4
5
6
7
8
9
10
11
T
VAA
12
13
14
15
Figure 3. Device Initialization for Transmit−only Mode
SCL must remain high for transmit−only mode
SCL
SDA
Bit8
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Don’t
(LSB) Care
Bit1
Bit8
Bit7
VCLK
T
VHIGH
T
VLOW
Figure 4. Transmit−Only Mode
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CAT24C21
Bi−Directional Mode (DDC2)
The following defines the features of the I
2
C bus protocol
Acknowledge
in bi−directional mode (Figure 5):
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
When in the bi−directional mode, all inputs to the VCLK
pin are ignored, except when a logic high is required to
enable write capability.
START Condition
The START condition (Figure 7) precedes all commands
to the device, and is defined as a HIGH to LOW transition
of SDA when SCL is HIGH. The CAT24C21 monitors the
SDA and SCL lines and will not respond until this condition
is met.
STOP Condition
After a successful data transfer, each receiving device is
required to generate an acknowledge (ACK). The
acknowledging device pulls down the SDA line during the
ninth clock cycle, signaling that it has received the 8 bits of
data (Figure 8).
The CAT24C21 responds with an ACK after receiving a
START condition and its slave address. If the device has
been selected along with a write operation, it responds with
an ACK after receiving each 8−bit byte.
When the CAT24C21 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line for
an ACK. Once it receives this ACK, the CAT24C21 will
continue to transmit data. If no ACK is sent by the Master,
the device terminates data transmission and waits for a
STOP condition.
Write Operations
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
VCLK must be held high in order to program the device.
This applies to byte write and page write operation. Once the
device is in its self−timed program cycle, VCLK can go low
and not affect programming.
Byte Write
The bus Master begins a transmission by sending a
START condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8−bit slave address are fixed as 1010
for the CAT24C21 (see Figure 9). The next three significant
bits are “don’t care”. The last bit of the slave address
specifies whether a Read or Write operation is to be
performed. When this bit is set to 1, a Read operation is
selected, and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24C21 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address. The CAT24C21 then
performs a Read or Write operation depending on the state
of the R/W bit.
t
F
t
LOW
SCL
t
SU:STA
SDA IN
t
AA
SDA OUT
t
HD:STA
t
HD:DAT
t
HIGH
In the Byte Write mode (Figure 10), the Master device
sends the START condition and the slave address
information (with the R/W bit set to zero) to the Slave
device. After the Slave generates an ACK, the Master sends
the byte address that is to be written into the address pointer
of the CAT24C21. After receiving another ACK from the
Slave, the Master device transmits the data byte to be written
into the addressed memory location. The CAT24C21
acknowledges once more and the Master generates the
STOP condition, at which time the device begins its internal
programming cycle to nonvolatile memory (Figure 6).
While this internal cycle is in progress, the device will not
respond to any request from the Master device.
t
R
t
LOW
t
SU:DAT
t
SU:STO
t
DH
t
BUF
Figure 5. Bus Timing
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