CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
Logical One Input Voltage
Logical Zero Input Voltage
Output HIGH Voltage
Output LOW Voltage
Input Leakage Current
Output Leakage Current
Standby Power Supply Current
Operating Power Supply Current
Input Capacitance
Output Capacitance
V
CC
= 5.0V
±5%,
T
A
= 0
o
C to 70
o
C
SYMBOL
V
IH
V
IL
V
OH
V
OL
I
I
I
O
I
CCSB
I
CCOP
CIN
CO
V
CC
= 5.25V
V
CC
= 4.75V
I
OH
= -6.5mA, V
CC
- 4.75V
I
OH
= +20.0mA, V
CC
= 4.75V
V
IN
= V
CC
or GND, V
CC
= 5.25V
V
OUT
= V
CC
or GND, V
CC
= 5.25V
V
IN
= V
CC
or GND, V
CC
= 5.25V Outputs Open
f = 5.0MHz, V
IN
= V
CC
or GND, V
CC
= 5.25V, Outputs
Open (Note 2)
FREQ = 1MHZ, V
CC
= Open, All Measurements are
Referenced to Device Ground
TEST CONDITIONS
MIN
2.0
-
2.4
-
-10
-10
-
-
-
-
MAX
-
0.8
-
0.5
-10
-10
500
12
12
12
UNITS
V
V
V
V
µA
µA
µA
mA
pF
pF
AC Electrical Specifications
PARAMETER
Clock to Data Out
Mux Select to Data Out
Input Setup Time (DO-7/10-7)
Input Hold Time (DO-7/10-7)
Output Enable Time
Output Disable Time
Clock Pulse Width
NOTES:
V
CC
= 5.0V
±5%,
T
A
= 0
o
C to 70
o
C (Note 3)
SYMBOL
t
PD
t
SELD
t
S
t
H
t
ENA
t
DIS
t
PW
(Note 4)
TEST CONDITIONS
MIN
-
-
10
3
-
-
10
MAX
21
20
-
-
20
13
-
UNITS
ns
ns
ns
ns
ns
ns
ns
2. Power supply current is proportional to frequency. Typical rating for I
CCOP
is 2.4mA/MHz.
3. AC Testing is performed as follows: Input levels: 0V and 3.0V, timing reference levels = 1.5V, input rise and fall times driven at 1ns/V, output
load C
L
= 40pF.
4. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major design and/or process
changes.
3
HSP9520, HSP9521
Timing Waveform
t
PW
CLOCK
(CLK)
t
S
INST
(I0 - I1)
t
S
DATA
(S0 - D7)
t
H
t
H
t
PW
MUX SEL
(S0 - S1)
t
PD
OUT
(Y0 - Y7)
t
SELD
THREE STATE
CONTROL
THREE STATE
OUTPUT
(Y0 - Y7)
OE
t
DIS
t
ENA
(HIGH IMPEDANCE)
1.7V
1.3V
1.5V
TABLE 1. INSTRUCTION CONTROL
I1
I0
HSP9520
HSP9521
S1
0
A1
B1
A1
B1
TABLE 2. REGISTER SELECT
S0
0
1
0
1
HSP9520 OR HSP9521
B2
B1
A2
A1
0
1
0
0
A2
B2
A2
B2
1
0
1
A1
B1
A1
B1
A2
B2
A2
B2
A1
B1
A1
B1
1
0
A2
B2
A2
B2
1
1
All Registers Hold
All Registers Hold
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
