HSP50306
February 1998
Digital QPSK Demodulator
Description
The HSP50306 is a 6-bit QPSK demodulator chip designed
for use in high signal to noise environments which have some
multipath distortion. The part recovers 2.048 MBPS data from
samples of a QPSK modulated 10.7MHz or 2.1MHz carrier.
The chip coherently demodulates the waveform, recovers
symbol timing, adaptively equalizes the signal to remove
multipath distortion, differentially decodes and multiplexes the
data decisions. 8-A lock signal is provided to indicate when
the tracking loops are locked and the data decisions are valid.
To optimize performance, a gain error feedback signal is
provided which can be filtered and used to close an I.F. AGC
loop around the A/D converter.
The QPSK demodulator derives all timing from CLKIN. The
chip divides this clock by 2 to provide the sample clock for the
external A/D converter. The -27 version operates at a clock
input of 26.97MHz and demodulates a 10.7MHz QPSK signal
to recover the 2048 KSPS data. The -25 version operates at a
clock input of 25.6MHz and demodulates a 2.1MHz QPSK
signal to recover the 2048 KSPS data. Variation from these
CLKIN frequencies will progressively degrade the receive
data rate, the receive IF, acquisition sweep rate, acquisition
sweep range and loop bandwidths as the deviation increases
from normal CLKIN. Details on the maximum allowable devia-
tion are found in the Input Characteristics section. The
HSP50306 processes 6-bit offset binary data. 4-bit data pro-
vides adequate performance for many applications.
Features
• 25.6MHz or 26.97MHz Clock Rates
• Single Chip QPSK Demodulator with 10kHz Tracking
Loop
• Square Root of Raised Cosine (
α
= 0.4) Matched
Filtering
• 2.048 MBPS Reconstructed Output Data Stream
• Bit Synchronization with 3kHz Loop Bandwidth
• Internal Equalization for Multipath Distortion
• 6-Bit Real Input: Digitized 10.7MHz or 2.1MHz IF
• Level Detection for External IF AGC Loop
• 0.1s Acquisition Time
• 10
-9
BER
• <116mA on +5.0V Supply
Applications
• Cable Data Link Receivers
• Cable Control Channel Receivers
Ordering Information
PART NUMBER
HSP50306SC-27
HSP50306SC-2796
HSP50306SC-25
HSP50306SC-2596
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
16 Ld SOIC
Tape and Reel
16 Ld SOIC
Tape and Reel
M16.3
PKG.
NO.
M16.3
Block Diagram
I
4 TAP
ADAPTIVE
EQUALIZER
I
COS
AGCOUT
ADCLK
CLKIN
RESET
TEST
CARRIER
LOOP FILTER
LEVEL
DETECT
SIN
NCO
TIMING
GENERATOR
BIT PHASE
DETECTOR
CARRIER
PHASE
DETECT
Q
DIFF.
DECODE/
MUX
DATAOUT
DIN0-5
6
Q
BIT SYNC
LOOP FILTER
LOCK
DETECT
LOCK
CLKOUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
4162.2
8-272
HSP50306
Pinout
16 LEAD SOIC
TOP VIEW
AGCOUT 1
CLKOUT 2
DATAOUT 3
LOCK 4
RESET 5
TEST 6
CLKIN 7
GND 8
16 V
CC
15 ADCLK
14 DIN0
13 DIN1
12 DIN2
11 DIN3
10 DIN4
9 DIN5
Pin Description
NAME
V
CC
GND
CLKIN
DIN (5:0)
SOIC PIN
16
8
7
9-14
TYPE
-
-
I
I
+5V Power Supply
Ground
Clock input. This is the processing clock for the part. All timing is derived from this clock.
I.F. input samples from the A/D converter. These bits interpreted as offset binary format. DIN5 is the
MSB. If fewer than 6 bits are used, the bits from the A/D should be connected to the MSBs of the
input and the unused LSBs grounded.
This output clock is the clock for the A/D converter.
This output indicates whether the magnitude of the input samples are above or below the expected
level. This output is provided as an error detector for an external AGC loop. The output is low when
the input is greater than nominal, and high when the input is lower than nominal.
This is the recovered data.
This is the recovered clock.
This signal indicates that the carrier tracking loop is locked and data on the DOUT pin should be valid.
This input is provided to for initialization and test. Active low.
This input is provided for test. Pull high for normal operation.
DESCRIPTION
ADCLK
AGCOUT
15
1
O
O
DATAOUT
CLKOUT
LOCK
RESET
TEST
3
2
4
5
6
O
O
O
I
I
8-273
HSP50306
The Block Diagram of the QPSK Demodulator is shown on
page 1. To demodulate the data, the I.F. samples are multi-
plied by sine and cosine samples from a numerically con-
trolled oscillator. The digital mixer outputs are then low pass
filtered to remove mixer products. The filtered data is then
equalized by a 4 tap equalizer (1 precursor, one reference tap,
and a 2 tap Decision Feedback Equalizer (DFE) to remove
distortion caused by multipath. The output of the equalizer is
differentially decoded and multiplexed into the output data
stream. The carrier tracking loop providing the L.O. for the dig-
ital mixer is a second order digital Costas loop with a tracking
bandwidth of ~10kHz. A sweep circuit searches the carrier
uncertainty using a triangle sweep algorithm during acquisi-
tion. A lock detector controls the sweep and indicates when
valid data is available. The recovered data rate clock is gener-
ated by another numerically controlled oscillator. The timing
recovery loop is a first order decision directed digital phase
locked with a loop bandwidth of
~
3kHz. The Level Detect cir-
cuitry generates the AGC error signal by rectifying the I.F.
input samples and comparing them against a threshold. The
error signal is low if the signal magnitude is above the upper
threshold, high if the magnitude is below the lower limit.
Figure 1 shows the circuit of a typical demodulator
application. The typical Bit Error Rate (BER) performance is
shown in Figure 2 for both 4-bit and 6-bit quantized inputs.
The theoretical QPSK BER Performance Curve is provided for
reference. Note that the BER performance shown in Figure 2
includes a multipath distortion element at the input, in addition
to the desired signal. This multipath distortion is
representative of receive signal distortions found in cable data
links.
Table 1 details the BER, Acquisition and Delay Performance
Specifications of the HSP50306 QPSK demodulator chip,
based on an input that complies with the specifications
detailed in Table 2.
Application Example
(25.6MHz)
26.97MHz
OSC
I.F. FILTER
DIGITIZED
10.7MHz (2.1MHz)
IF INPUT
CA3304/6
A/D
6
DIN0-5
ADCLK
AGCOUT
V+
RESET
LOCK
TEST
CLKIN
CLKOUT
2.048 MBPS
OUTPUT
DATA/CLK
HSP50306
DATAOUT
FIGURE 1. APPLICATIONS CIRCUIT EXAMPLE
0.01
0.001
0.0001
0.00001
1E-06
1E-07
1E-08
1E-09
1E-10
1E-11
1E-12
11
THEORETICAL
6-BIT DATA
4-BIT DATA
BIT ERROR RATE (BER)
12
13
14
15
16
17
E
S
/N
O
18
19
20
21
22
23
NOTE: Simulation performed using alpha = 0.4 Root Raised Cosine Transmit Filtering, Multipath -10dBc at 72
o
at 1.6µs.
FIGURE 2. TYPICAL BIT ERROR RATE PERFORMANCE
8-274
HSP50306
TABLE 1. PERFORMANCE SPECIFICATIONS
SPECIFICATION
BER
Acquisition Time
Carrier Loop Bandwidth
Bit Sync Loop Bandwidth
Throughput Delay
PERFORMANCE
Better than 1.0 x 10
-
9
with specified input signal characteristics. See Figure 1.
Acquisition within 0.1s from applying an input signal with the specified characteristics.
10kHz
3kHz
Less than 6 output bit times.
TABLE 2. INPUT SIGNAL CHARACTERISTICS
(NOTE 1)
PARAMETER
Carrier Frequency
Bit Rate
Modulation Format
10.7 x 10
6
±
40kHz.
2.048 x 10
6
±
0.01%.
QPSK w/differential encoding specified as:
00:
0
o
phase change
01: -90
o
phase change
Filtering
Input RMS Signal Level
Input Data Format
Input Clock Frequency
SINAD
Multipath Distortion
10: +90
o
phase change
11: 180
o
phase change (Note 2)
SPECIFICATION
Square root of raised cosine matched filtering (
α
= 0.4).
Set input p-p signal to full scale on the A/D converter.
6 bits, offset binary.
26.97MHz
±
0.015% (Note 3) for -27; 25.6MHz
±
0.015% for -25.
>25.5dB SNR (thermal (AWGN)), >28dB (adjacent channel interference).
Total energy in multipath distortion -10dBc
>95% of multipath energy within 2µs from main path. If the multipath changes rapidly, the bit error rate
may exceed the above specification until the equalizer has readjusted.
NOTES:
1. All frequencies are relative to the input clock frequency. For example, the bit rate is actually ~0.075936 * f
CLK
. The frequencies provided
in this document are only valid for a 26.97MHz or 25.6MHz clock.
2. Each pair of input bits is encoded into a phase change relative to the previous symbol. In the HSP50306, the symbol to symbol phase
change is decoded into the transmitted bit pair which is multiplexed into the output data stream.
3. While the device is static CMOS and can be clocked down to close to DC, the specified range indicates the accuracy needed to maintain
the data rate inside the bit sync tracking loop bandwidth assuming 50ppm tx and 100ppm rx crystal accuracies.
8-275
HSP50306
Two Versions: Different Applications
RECEIVE IF
DEMOD INPUT IF
The -27 and -25 versions of the HSP50306 Digital QPSK
Demodulator are not simply different speed grades of the
same device, but are designs which have proportionally
scaled clocks and bandwidths for different applications.
NOTE: While these parts are pin for pin compatible, in
most applications they cannot be used as functional
equivalent substitutes for each other.
Key differences are:
• The -27 version of the HSP50306 has an input IF of
10.7MHz with an input clock of 26. 97MHz.
DC 2.79
10.7 F
S
16.27
24.19 F
CLK
29.76
FIGURE 3. SAMPLED SPECTRUM FOR THE -27 VERSIONS
(f
CLK
= 26.97MHz)
DEMOD INPUT IF
RECEIVE IF
• The -25 version of the HSP50306 has an input IF of
2.1MHz with an input clock of 25. 6MHz.
In both the -27 and -25 designs, the sample rate clock for the
input IF signal is half of the CLK frequency.
NOTE: Sample
rate clock is designated by f
S
= f
CLK
/2.
Aside from input
IF and input clock, all other performance parameters of the
two parts are identical for their respective IF inputs.
DC
2.1
10.7 F
S
14.9
23.5 F
CLK
27.7
FIGURE 4. SAMPLED SPECTRUM FOR THE -25 VERSIONS
(f
CLK
= 25.6MHz)
10.7MHz Input IF Applications
Both the -27 and -25 parts can be used in 10.7MHz IF Applica-
tions. Figures 3 and 4 show the frequency spectrum for the
sampled 10.7MHz IF input signals for both the -27 and -25 ver-
sions, respectively. In the 10.7MHz IF Application, the -25 ver-
sion offers tighter filtering capability than the -27 version
because the lower IF allows use of low pass filtering. Also, the
lower IF of the -25 version has inherently lower internal pro-
cessing spectral spurs than the -27 version. Note that the
receive IF for the HSP50306SC-27 is the input IF to the demod-
ulator. For the HSP50306SC-25, the receive IF is 10.7MHz, but
the processing is done on the spectral image at 2.1MHz. Exam-
ine the spectral inversion between the 10.7MHz Receive IF and
the 2.1MHz demodulator input in Figure 4.
The transmit differ-
ential encoder must take into account this spectral rever-
sal.
The required encoding is shown in Table 3. This part was
designed to be paired with the HSP50307 Burst Modulator, and
can be operated from the same 25.6MHz reference clock.
TABLE 3. DIFFERENTIAL ENCODING REQUIRED FOR THE -27
AND -25 DEMODULATORS RECEIVING 10.7MHz IF
INPUT
BITS
00
01
10
11
PHASE CHANGE
REQUIRED FOR -27
DEMODULATION
0
o
-90
o
90
o
180
o
PHASE CHANGE
REQUIRED FOR -25
DEMODULATION
0
o
90
o
-90
o
180
o
8-276
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