HSP50215
Data Sheet
January 1999
File Number
4346.4
Digital UpConverter
The HSP50215 Digital UpConverter (DUC) is a QASK/FM
modulator/FDM upconverter designed for high dynamic range
applications such as cellular basestations. The DUC combines
shaping and interpolation filters, a complex modulator, and
Timing and Carrier NCO’s into a single package. Each DUC
can create a single FDM channel. Multiple DUC’s can be
cascaded digitally for multi-channel applications.
The HSP50215 supports both vector and FM modulation. In
vector modulation mode, the DUC accepts 16-bit I and Q
samples to generate virtually any quadrature AM or PM
modulation format. The DUC also has two FM modulation
modes. In the FM with pulse shaping mode, the 16-bit
frequency samples are pulse shaped/bandlimited prior to FM
modulation. No bandlimiting filter follows the FM modulator.
This FM mode is useful for GMSK type modulation formats. In
the FM with bandlimiting filter mode, the 16-bit frequency
samples directly drive the FM modulator. The FM modulator
output is filtered to limit the spectral occupancy. This FM mode
is useful for analog FM or FSK modulation formats.
The DUC includes an NCO driven interpolation filter, which
allows the input and output sample rate to have a non-
integer or variable relationship. This re-sampling feature
simplifies cascading modulators with sample rates that do
not have harmonic or integer frequency relationships.
The DUC offers digital output spectral purity that exceeds
85dB at the maximum output sample rate of 52 MSPS, for
input sample rates as high as 300 KSPS.
A 16-bit microprocessor compatible interface is used to load
configuration and baseband data. A programmable FIFO depth
interrupt simplifies the interface to the I and Q input FIFOs.
Features
• Output Sample Rates Up to 52 MSPS (48 MSPS
Industrial); Input Data Rates Up to 3.25 MSPS
• I/Q Vector, FM, and Shaped FM Modulation Formats
• 32-Bit Programmable Carrier NCO; 30-Bit Programmable
Symbol Timing NCO
• Programmable I and Q, 256 Tap, Shaping FIR Filters with
Interpolation by 4, 8 or 16
• Interpolation Filter Up Samples Shaping Filter Output to
Output Sample Rate Under NCO Control
• Processing Capable of >90dB SFDR
• Cascade Input for Multiple Channel Transmissions
• 16-Bit
µProcessor
Interface for Configuration and User
Data Input
Applications
• Single or Multiple Channel Digital Software Radio
Transmitters (Wide-Band or Narrow-Band)
• Base Station Transceivers
• Operates with HSP50214 in Software Radio Solutions
• Compatible with the HI5741 D/A Converter
• HSP50215EVAL Evaluation Board Available
Ordering Information
PART
NUMBER
HSP50215VC
HSP50215VI
TEMP
RANGE (
o
C)
0 to 70
-40 to 85
PACKAGE
100 Ld MQFP
PKG. NO
Q100 .14x20
s100 Ld MQFP Q100 .14x20
Block Diagram
†
=
µP
CONTROL SIGNALS
OUTPUT FORMATTER
CAS(15:0)
CASZ
IIN(15:0)
QIN(15:0)
1-7 DEEP
FIFO
†
†
QFIFO
MUX
GAIN
CTRL
MUX
LIMITER
IFIFO
SHAPING FILTER
INTERPOLATION
FILTER
+
+
OUT(15:0)
MUX
REFCLK
SYNCIN
FM
MOD
Q FM
RST
WR
RD
CE
C(15:0)
A(9:0)
CONTROL
QIN(15:0)
†
IIN(15:0)
†
CF(31:0)
†
SF(29:0)
†
OE
COS
SIN
I FM
OFM
NCO
CF(31:0)
NCO
†
SYNCOUT
FIFORDY
SAMPCLK
3-422
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
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Copyright
©
Intersil Corporation 1999
Functional Block Diagram
CAS(1P5:0)
CASZ
I FM
Q FM
MOD (1:0)
†
MUX
FM
MOD
MUX
1-7 DEEP
FIFO
OUTPUT FORMATTER
+
RTH (2:0)
†
EN_OUT
†
LIMITER
SHAPING
FILTER
LIMITER
SIN
COS
3-423
MUX
(-2dBFS)
0.8 MAX
(-3dBFS)
0.707
+
INTERPOLATION
FILTER
IFIFO
QFIFO
GAIN
CTRL
MOD (1:0)
†
MOD (1:0)
†
SET
CLOSE
TO LIMIT
NCO
COARSE
PHASE
NCO
FINE
PHASE
EnNCO
SR
CF
EN_OUT
MOD
OUTGAIN
FIFORDY
IFIFOEMPTY
QFIFOEMPTY
RTH
EnNCO
SYNCPOL
DS
IP
SYNC
IIN(15:0)
†
REFCLK
QIN(15:0)
†
OUT(15:0)
OFM
OE
RST
RST
†
MOD (1:0)
†
WR
RD
SR(29:0)
†
HSP50215
CE
C(15:0)
A(9:0)
ICOEFFICIENTS(15:0)
CONTROL
†
QCOEFFICIENTS(15:0)
†
CF(31:0)
†
OUTGAIN (7:0)
†
EN OUT
†
DLYSEL
†
DS (3:0)
†
IP (1:0)
†
FIFORDY
SAMPCLK
STATUS
SYNCPOL
†
SYNCSEL
†
CW3 WR
SYNCOUT
SYNCIN
†
=
µP
CONTROL SIGNALS
HSP50215
Pinout
100 LEAD MQFP
TOP VIEW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
OFM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FIFORDY
A0
A1
GND
A2
A3
A4
V
CC
A5
A6
A7
GND
A8
A9
WR
V
CC
CE
RD
RST
SYNCIN
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
OUT0
OUT15
OUT14
OUT13
OUT12
V
CC
OUT11
OUT10
OUT9
GND
OUT8
OE
OUT7
V
CC
OUT6
OUT5
OUT4
GND
OUT3
OUT2
OUT1
CASZ
CAS0
CAS1
GND
CAS2
CAS3
CAS4
CAS5
CAS6
CAS7
V
CC
GND
REFCLK
CAS8
CAS9
CAS10
CAS11
V
CC
CAS12
CAS13
CAS14
CAS15
C15
C14
C13
V
CC
C12
C11
C10
C9
GND
C8
C7
C6
C5
V
CC
C4
SAMPCK
C3
C2
GND
C1
C0
SYNCOUT
3-424
HSP50215
Pin Descriptions
NAME
V
CC
GND
C(15:0)
TYPE
-
-
I/O
+5V Power supply input.
Power supply ground input.
µP
Bidirectional Data bus. The C(15:0) bus is used for loading the configuration data and sample vectors for mod-
ulation. C15 is the MSB.
µP
Address Bus. The A(9:0) bus is used for addressing the proper registers for loading the configuration data and
sample vectors for modulation. A9 is the MSB.
µP
Write Strobe. When CE is asserted, data on the C(15:0) data bus is loaded into the address location found on
the A(9:0) bus on the rising edge of the WR signal. In some cases, there is an internal synchronization to the master
clock that must be completed before the next data is written. See the
µP
interface section for more information.
µP
Read Control. When RD and CE are low, the data found in the address location defined by A(9:0) is routed to
the C(15:0)
µP
data bus on the next rising edge of REFCLK.
µP
Chip Enable. Used to gate the WR and RD
µP
interface control signals.
FIFO Ready. A FIFORDY assertion indicates that the I and Q FIFOs have reached the programmed FIFO depth and
more samples are required to maintain that FIFO depth.
Reference Clock. REFCLK is the master clock for the DUC. All timing is relative to the REFCLK rising edge. The
frequency of the reference clock is denoted f
CLK
, and is the rate at which data is output from the part.
Cascade Input Bus. This input bus is used to cascade multiple parts by routing the digital modulated signal from
one DUC into the output summer of a second DUC. CAS(15:0) is 2’s complement format and is sampled on the
rising edge of REFCLK. CAS15 is the MSB.
Cascade Input Bus Zero. When CASZ is asserted (pulled high), the part places zeroes on the CAS(15:0) data path.
CASZ is asynchronous (not registered) to REFCLK and should not be changed on the fly. When unused, pull high
with a pull up resistor (~22kΩ).
Output Data Bus. OUT(15:0) contains the digital modulated DUC output samples and is updated on the rising edge
of the REFCLK. OUT15 is the MSB.
Output Data Bus Format. When OFM is asserted (pulled high), the output bus format is 2’s complement. When not
asserted, the output format is offset binary. The OFM input is asynchronous (not registered) to REFCLK and should
not be changed on the fly.
Output Data Bus Enable. When OE is asserted (dropped low), the output data bus OUT(15:0) is enabled. When OE
is not asserted (pulled high), the output data bus OUT(15:0) is placed in the high impedance state.
Sync Input. The SYNCIN input is used to synchronize the processing of multiple parts. The SYNCOUT of one part
acts as a master and is connected to the SYNCIN of all of the DUC’s that are to by synchronized. The DUC can be
programmed so that either rising or falling edge of this signal initiates the processing.
Sync Output. The SYNCOUT output is used to synchronize the processing of multiple parts. The SYNCOUT of one
part acts as a master, and is connected to the SYNCIN of all of the DUC’s that are to be synchronized.
Sample Clock. This clock is provided to the data source to indicate when data is being transferred from the FIFO to
the shaping filter. The SAMPCLK output is generated by the sample rate NCO when the digital filter takes a new
sample. It has approximately 50% duty cycle. The sample is taken on the high-to-low transition. SAMPCLK may be
used instead of FIFORDY.
Reset. When the RST input is asserted (dropped low), the DUC is reset and all processing halts. The DUC may
also be reset on
µP
command. Processing remains halted until a sync is generated either by
µP
command or
assertion of SYNCIN. See the Reset section details of the specific functions halted by this control signal.
DESCRIPTION
A(9:0)
I
WR
I
RD
I
CE
FIFORDY
I
O
REFCLK
I
CAS(15:0)
I
CASZ
I
OUT(15:0)
O
OFM
I
OE
I
SYNCIN
I
SYNCOUT
O
SAMPCLK
O
RST
I
3-425
HSP50215
Functional Description
The HSP50215 Digital UpConverter (DUC) converts digital
baseband data into modulated or frequency translated digital
samples. The DUC can be configured to create any
quadrature amplitude shift-keyed (QASK) data modulated
signal, including QPSK, BPSK, and m-ary QAM. The DUC
can also be configured to create both shaped and unfiltered
FM signals. A minimum of 16 bits of resolution is maintained
throughout the internal processing.
The DUC is configured via the 16-bit microprocessor data
bus, using the address bus and RD, WR and CE control
signals. Configuration data that is loaded via this bus
includes the 30-bit Sample Rate NCO center frequency, the
32-bit Carrier NCO center frequency, the modulation format,
gain control, FIFO control, reset control and sync control.
The I and Q baseband channels each have a 256 tap FIR
filter whose coefficients and configuration are also
programmed via the
µP
interface. Similarly, the control
signals for the I and Q channel interpolation filters are
programmed via the
µP
interface. Once the operational
configuration for the device has been set, the 16-bit
µP
interface is used to input the I and Q data into the associated
FIFOs.
The FIFOs provide the data interface between the
µP
and
either the FM modulator or the shaping filters. Multiplexers
route the I data to the FM modulator in the FM with
bandlimiting filter mode. Both I and Q are routed to the 256
tap FIR shaping filters in the QASK mode. The shaping filter
serves to both shape and interpolate the sample rate to 4, 8,
or 16 times the input sample rate. The I shaping filter output
can also be routed to the FM modulator for the FM with pulse
shaping mode. Multiplexers select either the FM modulator
output or the shaping filter output to be scaled and routed to
the interpolation filters.
The I and Q interpolation filters allow a non-integer increase in
sample rate, up to the reference clock rate. The interpolation
filter output data is upconverted or modulated by the Carrier
NCO and multipliers. The modulated signal is added to
modulated inputs from other cascaded DUC’s. The output
formatter sets the output buffer state and the output data
format.
A(000)
WR
DFF1
R
E
G
DFF2
R
E
G
DFF3
R
E
G
DFF4
R
E
G
>
>
>
>
†
ALL REGISTERS
ARE CLOCKED AT
REFCLK UNLESS
SHOWN OTHERWISE
IIN(15:0)
R
E
G
WRITE SHIFT ENABLE
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
>
WR
>
>
>
>
>
>
>
ZERO’S
A(2:0)
COMP
8:1 MUX
IFIFO(15:0)
RTH(2:0)
DFF
COMP
FIFORDY
QFIFO(15:0)
FM ENABLED
QIN(15:0)
1
8:1 MUX
>
WR
R
E
G
>
R
E
G
>
R
E
G
0
R
E
G
>
>
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
WRITE SHIFT ENABLE
DFF1
DFF2
R
E
G
DFF3
R
E
G
DFF4
R
E
G
A(001)
WR
>
R
E
G
>
>
>
FIGURE 1. I AND Q FIFO BLOCK DIAGRAM
WR
1
REFCLK
DLY DATA
DFF 1
DFF 2
DFF 3
DFF 4
WR SHFT EN
REG1
FIFO NEEDS
FIFORDY MORE DATA
FIFO NEEDS
MORE DATA
2
3
4
Programmable FIFO
The Programmable FIFOs provide a data storage and
interface between the microprocessor data write holding
register and the shaping filter or the FM modulator. Signal
routing out of the FIFO is set by the modulation format. Each
FIFO has seven 16-bit registers. Figure 1 shows the
conceptual details of the I and Q FIFOs.
FIGURE 2. FIFORDY AND DATA DELAY TIMING
3-426
FPGA/CPLD
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