HSP50214A
December 1999
OUTPUT FORMATTER
[ /Title
(HSP5
0214A
)
/Sub-
ject (
Pro-
gram-
mable
Down-
con-
verter)
/Autho
r ()
/Key-
words
(Inter-
sil
Semi-
con-
ductor,
Down-
con-
verter,
Down
Con-
verter,
Pro-
gram-
mable
Down-
con-
verter,
DSP,
AMPS,
TDMA
, North
Ameri-
can
PO
T
CT
DUC
PRO PRODU
E
LET
TE
BSO BSTITU
O
B
E SU
0214
SIBL HSP5
S
Programmable Downconverter
Description
The HSP50214A Programmable Downconverter converts dig-
itized IF data into filtered baseband data which can be pro-
cessed by a standard DSP microprocessor. The
Programmable Downconverter (PDC) performs down conver-
sion, decimation, narrowband low pass filtering, gain scaling,
resampling, and Cartesian to Polar coordinate conversion.
The 14-bit sampled IF input is down converted to baseband
by digital mixers and a quadrature NCO, as shown in the
Block Diagram. A decimating (4 to 32) fifth order Cascaded
Integrator-Comb (CIC) filter can be applied to the data
before it is processed by up to 5 decimate-by-2 halfband fil-
ters. The halfband filters are followed by a 255-tap pro-
grammable FIR filter. The output data from the
programmable FIR filter is scaled by a digital AGC before
being re-sampled in a polyphase FIR filter. The output sec-
tion can provide seven types of data: Cartesian (I, Q), polar
(R, q), filtered frequency (dq/dt), Timing Error (TE), and
AGC level in either parallel or serial format.
Features
• Up to 65 MSPS Front-End Processing Rates (CLKIN) and
55 MSPS (41 MSPS Using the Discriminator) Back-End
Processing Rates (PROCCLK)
Clocks May Be Asynchronous
• Processing Capable of >100dB SFDR
• Up to 255-Tap Programmable FIR
• Overall Decimation Factor Ranging from 4 to 16384
• Output Samples Rates to
≅12.94
MSPS with Output Band-
widths to
≅
982kHz Lowpass
• 32-Bit Programmable NCO for Channel Selection and Car-
rier Tracking
• Digital Resampling Filter for Symbol Tracking Loops and
Incommensurate Sample-to-Output Clock Ratios
• Digital AGC with Programmable Limits and Slew Rate to
Optimize Output Signal Resolution; Fixed or Auto Gain
Adjust
• Serial, Parallel, and FIFO 16-Bit Output Modes
• Cartesian to Polar Converter and Frequency Discriminator
for AFC Loops and Demodulation of AM, FM, FSK, and
DPSK
• Input Level Detector for External I.F. AGC Support
Ordering Information
PART
NUMBER
HSP50214AVC
HSP50214AVI
TEMP.
RANGE (
o
C)
0 to 70
-40 to 85
PACKAGE
120 Ld MQFP
120 Ld MQFP
PKG. NO.
Q120.28x28
Q120.28x28
Applications
• Single Channel Digital Software Radio Receivers
• Base Station Rx’s: AMPS, NA TDMA, GSM, and CDMA
• Compatible with HSP50210 Digital Costas Loop for PSK
Reception
• Evaluation Platform Available
Block Diagram
MICROPROCESSOR
READ/WRITE
C(7:0)
LEVEL DETECT
HALFBAND
FILTERS
5
TH
ORDER
CIC
FILTER
5
TH
ORDER
CIC
FILTER
CARRIER
NCO
RESAMPLING
NCO
DISCRIMINATOR
FREQ
255-TAP
FIR FILTER
I OUT
POLYPHASE
FIR AND
HALFBAND
FILTERS
POLYPHASE
FIR AND
HALFBAND
FILTERS
SEROUTA
CARTESIAN
TO
POLAR
COORDINATE
CONVERTER
Q OUT
MAG.
SEROUTB
AOUT(15:0)
BOUT(15:0)
CONTROL
AGC LOOP FILTER
AGC
IN(13:0)
GAIN
ADJ
(2:0)
COF
SOF
CLKIN
PROCCLK
REFCLK
INPUT
SECTION
HALFBAND
FILTERS
255-TAP
FIR FILTER
PHASE
TIMING ERROR
∆
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Copyright
©
Intersil Corporation 1999
File Number
4449.1
1
HSP50214A
Pinout
120 LEAD MQFP
TOP VIEW
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
IN11
IN12
IN13
AGCGNSEL
V
CC
REFCLK
GND
OEAH
AOUT15
AOUT14
AOUT13
AOUT12
AOUT11
AOUT10
GND
NC
AOUT9
AOUT8
AOUT7
AOUT6
AOUT5
V
CC
NC
AOUT4
AOUT3
AOUT2
AOUT1
AOUT0
GND
OEAL
IN10
IN9
IN8
GND
IN7
NC
IN6
IN5
IN4
IN3
IN2
GND
IN1
IN0
V
CC
CLKIN
GND
NC
ENI
GAINADJ2
GAINADJ1
GAINADJ0
COF
COFSYNC
GND
SOF
SOFSYNC
V
CC
SYNCIN1
SYNCIN2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
DATARDY
OEBH
BOUT15
BOUT14
V
CC
NC
BOUT13
BOUT12
BOUT11
BOUT10
BOUT9
BOUT8
GND
GND
PROCCLK
V
CC
MSYNCI
MSYNCO
GND
BOUT7
BOUT6
BOUT5
GND
BOUT4
NC
BOUT3
BOUT2
BOUT1
BOUT0
OEBL
SYNCOUT
INTRRP
WR
RD
GND
C7
C6
NC
C5
C4
V
CC
C3
C2
C1
NC
C0
A2
A1
A0
GND
SEL2
SEL1
SEL0
GND
SEROUTA
SEROUTB
SERSYNC
SEROE
SERCLK
V
CC
2
HSP50214A
Pin Descriptions
NAME
V
CC
GND
CLKIN
IN(13:0)
ENI
TYPE
-
-
I
I
I
Positive Power Supply Voltage.
Ground.
Input Clock. This clock should be a multiple of the input sample rate. All input section processing oc-
curs on the rising edge of CLKIN. The frequency of CLKIN is designated f
CLKIN
.
Input Data. The format of the input data may be set to offset binary or 2’s complement. IN13 is the
MSB (see Control Word 0).
Input Enable. Active Low. This pin enables the input to the part in one of two modes, gated or inter-
polated (see Control Word 0). In gated mode, one sample is taken per CLKIN when ENI is asserted.
The input sample rate is designated f
S
, which can be different from f
CLKIN
When ENI is used.
GAINADJ Input. Adds an offset to the gain via the shifter following the mixer. GAINADJ value is added
to the shift code from the microprocessor (µP) interface. The shift code is saturated to a maximum
code of F. The gain is offset by (6dB)(GAINADJ); (000 = 0dB gain adjust; 111 = 42dB gain adjust)
GAINADJ2 is the MSB. See “Using the Input Gain Adjust Control Signals” Section.
Processing Clock. PROCCLK is the clock for all processing functions following the CIC Section. Pro-
cessing is performed on PROCCLK’s rising edge. All output timing is derived from this clock.
NOTE: This clock may be asynchronous to CLKIN.
AGC Gain Select. This pin selects between two AGC loop gains. This input is setup and held relative
to PROCCLK. Gain setting 1 is selected when AGCGNSEL = 1.
Carrier Offset Frequency Input. This serial input pin is used to load the carrier offset frequency into the
Carrier NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup and hold
times are relative to CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1].
Carrier Offset Frequency Sync. This signal is asserted one CLK before the most significant bit (MSB)
of the offset frequency word (see Serial Interface Section). The setup and hold times are relative to
CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1].
Re-Sampler Offset Frequency Input. This serial input pin is used to load the offset frequency into the
Re-Sampler NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup
and hold times are relative to PROCCLK. This input is compatible with the output of the HSP50210
Costas loop [1].
Re-Sampler Offset Frequency Sync. This signal is asserted one CLK before the MSB of the offset
frequency word (see Serial Interface Section). The setup and hold times are relative to PROCCLK.
This input is compatible with the output of the HSP50210 Costas loop [1].
Parallel Output Bus A. Two parallel output modes are available on the HSP50214A. The first is called
the Direct Output Port, where the source is selected through Control Word 20 (see the Microproces-
sor Write Section) and comes directly from the Output MUX Section (see Output Control Section).
The most significant byte of AOUT always outputs the most significant byte of the Parallel Direct Out-
put Port whose data type is selected via
µP
interface. AOUT15 is the MSB. In this mode, the
AOUT(15:0) bus is updated as soon as data is available. DATARDY is asserted to indicate new data.
The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port
acts like a FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude, phase,
and frequency information; a data type is selected using SEL(2:0). Up to 7 data sets are stored in the
Buffer RAM Output Port. The LSBytes of the AOUT and BOUT busses form the 16 bits for the buffered
output mode and can be used for buffered mode while the MSBytes are outputting data in the direct
output mode.
BOUT(15:0)
O
Parallel Output Bus B. Two parallel output modes are available on the HSP50214A. The first is called
the Direct Output Port, where the source is selected through Control Word 20 (see the Microproces-
sor Write Section) and comes directly from the Output MUX Section (see Output Control Section).
The most significant byte of BOUT always outputs the most significant byte of the Parallel Direct Out-
put Port whose data type is selected via
µP
interface. BOUT15 is the MSB. In this mode, the
BOUT(15:0) bus is updated as soon as data is available. DATARDY is asserted to indicate new data.
The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port
acts like a FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude, phase,
and frequency information; a particular information is selected using SEL(2:0). Up to 7 data sets is
stored in the Buffer RAM Output Port. The least significant byte of BOUT can be used to either output
the least significant byte of the B Parallel Direct Output Port or the least significant byte of the Buffer
RAM Output Port. See Output Section.
DESCRIPTION
GAINADJ(2:0)
I
PROCCLK
I
AGCGNSEL
COF
I
I
COFSYNC
I
SOF
I
SOFSYNC
I
AOUT(15:0)
O
3
HSP50214A
Pin Descriptions
NAME
DATARDY
(Continued)
DESCRIPTION
Output Strobe Signal. Active Low. Indicates when new data from the Direct Output Port Section is
available. DATARDY is asserted for one PROCCLK cycle during the first clock cycle that data is avail-
able on the parallel out busses. See Output Section.
Output enable for the MSByte of the AOUT bus. Active Low.
Output enable for the LSByte of the AOUT bus. Active Low.
Output enable for the MSByte of the BOUT bus. Active Low.
Output enable for the LSByte of the BOUT bus. Active Low.
Select Address is used to choose which information in a data set from the Buffer RAM Output Port is
sent to the least significant bytes of AOUT and BOUT. SEL2 is the MSB.
Interrupt Output. Active Low. This output is asserted for 8 PROCCLK cycles when the Buffer RAM
Output Port is ready for reading.
Serial Output Bus A Data. I, Q, magnitude, phase, frequency, timing error and AGC information can
be sequenced in programmable order. See Output Section and Microprocessor Write Section.
Serial Output Bus B Data. Contents may be related to SEROUTA. I, Q, magnitude, phase, frequency,
timing error and AGC information can be sequenced in programmable order. See Output Section and
Microprocessor Write Section.
Output Clock for Serial Data Out. Derived from PROCCLK as given by Control Word 20 in the Micro-
processor Write Section.
Serial Output Sync Signal. Serves as serial data strobes. See Output Section and Microprocessor
Write Section.
Serial Output Enable. When high, the SEROUTA, SEROUTB, SERCLK, and SERSYNC signals are
set to a high impedance.
Processor Interface Data Bus. See Microprocessor Write Section. C7 is the MSB.
Processor Interface Address Bus. See Microprocessor Write Section. A2 is the MSB.
Processor Interface Write Strobe. C(7:0) is written to Control Words selected by A(2:0) in the Pro-
grammable Down Converter on the rising edge of this signal. See Microprocessor Write Section.
Processor Interface Read Strobe. C(7:0) is read from output or status locations selected by A(2:0)
in the Programmable Down Converter on the falling edge of this signal. See Microprocessor Read
Section.
Reference Clock. Used as an input clock for the timing error detector. The timing error is computed
relative to REFCLK. REFCLK frequency must be less than or equal to PROCCLK/2.
Multiple Chip Sync Output. Provided for synchronizing multiple parts when CLKIN and PROCCLK are
asynchronous. MSYNCO is the synchronization signal between the input section operating under
CLKIN and the back end processing operating under PROCCLK. This output sync signal from one
part is connected to the MSYNCI signal of all the HSP50214As.
Multiple Chip Sync Input. The MSYNCI pin of all the parts should be tied to the MSYNCO of one part.
NOTE: MSYNCI must be connected to an MSYNCO signal for operation.
SYNCIN1
I
CIC Decimation/Carrier NCO Update Sync. Can be used to synchronize the CIC Section, carrier NCO
update, or both. See the Multiple Chip Synchronization Section and Control Word 0 in the Micropro-
cessor Write Section. Active High.
FIR/Timing NCO Update/AGC Gain Update Sync. Can be used to synchronize the FIR, Timing NCO
update, AGC gain update, or any combination of the above. See the Multiple Chip Synchronization
Section and Control Words 7, 8, and 10 in the Microprocessor Write Section. Active High.
Strobe Output. This synchronization signal is generated by the
µP
interface for synchronizing multiple
parts. Can be generated by PROCLK or CLKIN (see Control Word 0 and Control Word 24 in the Mi-
croprocessor Write Section). Active High.
TYPE
O
OEAH
OEAL
OEBH
OEBL
SEL(2:0)
INTRRP
SEROUTA
SEROUTB
I
I
I
I
I
O
O
O
SERCLK
SERSYNC
SEROE
C(7:0)
A(2:0)
WR
RD
O
O
I
I/O
I
I
I
REFCLK
MSYNCO
I
O
MSYNCI
I
SYNCIN2
I
SYNCOUT
O
4
AGCGNSEL
AGCOUT
LIMIT
A
LOOP
FILTER
ERROR
DETECT
TO OUTPUT FORMATTER
AND MICROPROCESSOR
INTERFACE
PROCCLK
CLKIN
GAINADJ(2:0)
ENI
CARTESIAN
TO
POLAR
I
DATARDY
INTRRP
255-TAP
PROGRAMMABLE
FIR FILTER
(DECIMATE UP TO 16)
AGC
RE-SAMPLER
INTERPOLATE
BY 2/4
HALFBAND
FILTERS
2
2
I +Q
Q
atan
---
I-
AOUT(15:0)
BOUT(15:0)
INPUT
SECTION
SHIFT
(C
O
= 1;
C
n
= 0)
LEVEL
DETECT
MIXER
5TH ORDER
CIC
DECIMATE
FROM 4-32
0 TO 5 HALFBAND FILTER;
DECIMATION UP TO 32
TO
µPROCESSOR
INTERFACE
POLYPHASE
FILTER
IN(13:0)
Q
OEAH
OEAL
OEBH
OEBL
SHIFT
SIN
COS
POLYPHASE
FILTER
COF
(C
O
= 1;
C
n
= 0)
HSP50214A
COFSYNC
(SYMBOL TRACKING)
NCO
NCO
OUTPUT FORMATTER
DISCRIMINATOR
63-TAP
dθ
PROGRAMMABLE
FIR FILTER
d
t
5
OUTPUT SECTION
DISCRIMINATOR SECTION
INPUT SECTION
LEVEL DETECT SECTION
SYNCHRONIZATION SECTION
CARRIER NCO SECTIONS
CIC, HALFBAND FILTER, AND FIR SECTIONS
DIGITAL AGC SECTION
RE-SAMPLER/INTERPOLATION HALFBAND SECTION
TIMING NCO
INTRRP
SEL(2:0)
(CARRIER TRACKING)
SEROUTA
SEROUTB
TIMING ERROR
DIFFERENCE
A
CLKIN
PROCCLK
AGCOUT
SERCLK
SERSYNC
SEROE
MSYNCI
CHIP
SYNCHRONIZATION
CIRCUITRY
SYNCOUT
MSYNCO
SOF
SOFSYNC
REFCLK
MICROPROCESSOR
READ/WRITE
RD
WR
A(2:0)
CONTROL
SECTION
BACK END
SYNCHRONIZATION
CIRCUITRY
SYNCIN2
C(7:0)
FRONT END
SYNCHRONIZATION
CIRCUITRY
SYNCIN1
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50214A PROGRAMMABLE DOWNCONVERTER
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