HSP50210
Data Sheet
January 1999
File Number
3652.4
Digital Costas Loop
The Digital Costas Loop (DCL) performs many of the
baseband processing tasks required for the demodulation of
BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM
waveforms. These tasks include matched filtering, carrier
tracking, symbol synchronization, AGC, and soft decision
slicing. The DCL is designed for use with the HSP50110
Digital Quadrature Tuner to provide a two chip solution for
digital down conversion and demodulation.
The DCL processes the In-phase (I) and quadrature (Q)
components of a baseband signal which have been digitized
to 10 bits. As shown in the block diagram, the main signal
path consists of a complex multiplier, selectable matched
filters, gain multipliers, cartesian-to-polar converter, and soft
decision slicer. The complex multiplier mixes the I and Q
inputs with the output of a quadrature NCO. Following the
mix function, selectable matched filters are provided which
perform integrate and dump or root raised cosine filtering
(α ~ 0.40). The matched filter output is routed to the slicer,
which generates 3-bit soft decisions, and to the cartesian-to-
polar converter, which generates the magnitude and phase
terms required by the AGC and Carrier Tracking Loops.
The PLL system solution is completed by the HSP50210
error detectors and second order Loop Filters that provide
carrier tracking and symbol synchronization signals. In
applications where the DCL is used with the HSP50110,
these control loops are closed through a serial interface
between the two parts. To maintain the demodulator
performance with varying signal power and SNR, an internal
AGC loop is provided to establish an optimal signal level at
the input to the slicer and to the cartesian-to-polar converter.
Features
• Clock Rates Up to 52MHz
• Selectable Matched Filtering with Root Raised Cosine or
Integrate and Dump Filter
• Second Order Carrier and Symbol Tracking Loop
Filters
• Automatic Gain Control (AGC)
• Discriminator for FM/FSK Detection and Discriminator
Aided Acquisition
• Swept Acquisition with Programmable Limits
• Lock Detector
• Data Quality and Signal Level Measurements
• Cartesian to Polar Converter
• 8-Bit Microprocessor Control - Status Interface
• Designed to work with the HSP50110 Digital
Quadrature Tuner
• 84 Lead PLCC
Applications
• Satellite Receivers and Modems
• BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM
Demodulators
• Digital Carrier Tracking
• Related Products: HSP50110 Digital Quadrature Tuner,
D/A Converters HI5721, HI5731, HI5741
• HSP50110/210EVAL Digital Demod Evaluation Board
Block Diagram
CARRIER
TRACK
CONTROL
HI/LO
(COF)
CARRIER ACQ/TRK
LOOP FILTER
NCO
COS SIN
I SER OR
I
IN
(9-0)
SERCLK
OR CLK
Q SER OR
Q
IN
(9-0)
SYMBOL
TRACK
CONTROL
CONTROL/
STATUS
BUS
(SOF)
10
Q
10
I
RRC
FILTER
INTEGRATE/
DUMP
INTEGRATE/
DUMP
8
CARTESIAN
TO
POLAR
8 MAGNITUDE
8
PHASE
3
SLICER
3
Q
I
LOOP
FILTER
CARRIER PHASE
ERROR DETECT
LEVEL
DETECT
DATA PATH MULTIPLEXER
LOCK
DETECT
LKINT
THRESH
A
OUT(9-0)
10
LEVEL
DETECT
8
RRC
FILTER
10
B
OUT(9-0)
SMBLCLK
OEA
OEB
SYMBOL
TRACKING
LOOP FILTER
13
CONTROL
INTERFACE
SYMBOL
PHASE
ERROR
DETECT
3-253
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
HSP50210
Pinout
84 LEAD PLCC
TOP VIEW
SLOCLK
SERCLK
THRESH
GND
SSYNC
AOUT9
AOUT8
AOUT7
AOUT6
AOUT5
AOUT4
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
COFSYNC
WR
FZ-ST
LKINT
COF
RD
VCC
A2
A1
A0
C7
C6
C5
C4
C3
C2
C1
FZ-CT
GND
GND
C0
QSER
HI/LO
ISER
GND
OEA
VCC
4
IIN6
IIN7
IIN8
IIN9
8
11 10 9
IIN5
IIN4
IIN3
IIN2
GND
IIN1
IIN0
SYNC
QIN9
QIN8
QIN7
QIN6
QIN5
QIN4
VCC
QIN3
QIN2
QIN1
QIN0
SOFSYNC
SOF
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
7
6
5
3
2
1 84 83 82 81 80 79 78 77 76 75
AOUT3
AOUT2
AOUT1
AOUT0
SMBLCLK
VCC
CLK
GND
BOUT9
BOUT8
BOUT7
BOUT6
BOUT5
GND
BOUT4
BOUT3
BOUT2
BOUT1
BOUT0
OEB
VCC
Ordering Information
PART NUMBER
HSP50210JC-52
HSP50210JI-52
TEMP.
RANGE (
o
C)
0 to 70
-40 to 85
PACKAGE
84 Lead PLCC
84 Lead PLCC
PKG.
NO.
N84.1.15
N84.1.15
3-254
HSP50210
Pin Description
NAME
V
CC
GND
IIN9-0
QIN9-0
SYNC
COF
TYPE
-
-
I
I
I
O
+5V Power Supply.
Ground.
In-Phase Parallel Input. Data may be two’s complement or offset binary format (see Table 14). These inputs are
sampled by CLK when the SYNC signal is active Low. IIN9 is the MSB. See Input Controller Section.
Quadrature Parallel Input. Data may be two’s complement or offset binary format (see Table 14). These inputs are
sampled by CLK when the SYNC signal is active Low. QIN9 is the MSB. See Input Controller Section.
Data Sync. When SYNC is asserted “Low”, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the
rising edge of CLK.
Carrier Offset Frequency. The frequency term generated by the Carrier Tracking Loop Filter is output serially via this
pin. The new offset frequency is shifted out MSB first by CLK or SLOCLK starting with the clock cycle after the
assertion of COFSYNC.
Carrier Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial data
word. (Programmable Polarity, see Table 41, bit 11).
Sampler Offset Frequency. Sample frequency correction term generated by the Symbol Tracking Loop Filter is output
serially via this pin. The frequency word is shifted out MSB first by CLK or SLOCLK starting with the clock cycle after
assertion of SOFSYNC.
Sampler Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial
data word. (Programmable Polarity, see Table 41, bit 12).
Address Bus. The address on these pins specify a target register for reading or writing (see Microprocessor Interface
Section). A0 is the LSB.
Microprocessor Interface Data Bus. This bi-directional bus is used for reading and writing to the processor interface.
These are the data I/O pins for the processor interface. C0 is the LSB.
Write. This is the write strobe for the processor interface (see Microprocessor Interface Section).
Read. This is the read enable for the processor interface (see Microprocessor Interface Section).
Freeze Symbol Tracking Loop. Asserting this pin “high” zeroes the sampling error into the Symbol Tracking Loop
Filter (see Symbol Tracking Loop Filter Section).
Freeze Carrier Tracking Loop. Asserting this pin “high” zeroes the carrier Phase Error input to the Carrier Tracking
Loop Filter.
Lock Detect Interrupt. This pin is asserted “high” for at least 4 CLK cycles when the Lock Detector Integration cycle
is finished (see Lock Detector Section). Used as an interrupt for a processor. The Lock Detect Interrupt may be
asserted “high” longer than 4 CLK cycles, depending on the Lock Detector mode.
Threshold Exceeded. This output is asserted “low” when the magnitude out of the Cartesian to Polar converter
exceeds the programmable Power Detect Threshold (see Table 15 and AGC Section).
Slow Clock. Optional serial clock used for outputting data from the Carrier and Symbol Tracking Loop Filters. The
clock is programmable and has a 50% duty cycle.
Note: Not used when the HSP50110 is used with the
HSP50210 (see Table 41).
In-Phase Serial Input. Serial data input for In-Phase Data. Data on this pin is shifted in MSB first and is synchronous
to SERCLK (see Input Controller Section).
Quadrature Serial Input. Serial data input for Quadrature Data. Data on this pin is shifted in MSB first and is
synchronous to SERCLK (see Input Controller Section).
Serial Word Sync. This input is asserted “high” one CLK before the first data bit of the serial word (see Figure 2).
Serial Clock. May be asynchronous to other clocks. Used to clock in serial data (see Input Controller Section).
A Output. Data on this output depend on the configuration of Output Selector. AOUT9 is the MSB (see Table 42).
B Output. Data on this output depend on the configuration of Output Selector. BOUT9 is the MSB (see Table 42).
Symbol Clock. 50% duty cycle clock aligned with soft bit decisions (see Figure 19).
A Output Enable. This pin is the three-state control pin for the AOUT9-0. When OEA is high, the AOUT9-0 is high
impedance.
B Output Enable. This pin is the three-state control pin for the BOUT9-0. When OEB is high, the AOUT9-0 is high
impedance.
HI/LO. The output of the Input Level Detector is provided on this pin (see Input Level Detector Section). This signal
can be externally averaged and used to control the gain of an amplifier to close an AGC loop around the A/D con-
verter. This type of AGC sets the level based on the median value on the input.
System Clock. Asynchronous to the processor interface and serial inputs.
DESCRIPTION
COFSYNC
SOF
O
O
SOFSYNC
A2-0
C7-0
WR
RD
FZ_ST
FZ_CT
LKINT
O
I
I/O
I
I
I
I
O
THRESH
SLOCLK
O
O
ISER
QSER
SSYNC
SERCLK
AOUT9-0
BOUT9-0
SMBLCLK
OEA
OEB
HI/LO
I
I
I
I
O
O
O
I
I
0
CLK
I
3-255
AGC
LOOP
FILTER
GAIN ERROR
DETECT
THRESH
HI/LO
MATCHED FILTERING
CARTESIAN
TO
POLAR
SMBLCLK
I&D
I
2
+Q
2
M
U
X
LEVEL
DETECT
SYNC
RRC
M
U
X
M
U
X
COS
SIN
ISER
SLICER
QSER
INPUT CONTROLLER
3-256
RRC
I&D
M
U
X
M
U
X
M
U
X
TAN
-1
( Q )
I
SYMBOL TRACKING
2ND ORDER LOOP
FILTER
SYMBOL PHASE
ERROR DETECT
AOUT9-0
CARRIER TRACKING
2ND ORDER LOOP
FILTER
CARRIER PHASE
ERROR DETECT
OEA
OEB
ACQUISITION
CONTROL
DISCRIMINATOR
FREQUENCY
ERROR DETECT
d
dt
BOUT9-0
FROM
LOCK
DETECTOR
LOCK
DETECT
LKINT
IIN9-0
SYNTHESIZER/
MIXER
QIN9-0
I
SSYNC
Q
SERCLK
NCO
SOFSYNC
SOF
COFSYNC
HSP50210
COF
SERIAL
OUTPUT
FORMATTER
SLOCLK
8
C7-0
WR
RD
A2-0
MICROPROCESSOR
INTERFACE
CLK
FRZ_ST
FRZ_CT
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50210
HSP50210
Functional Description
The HSP50210 Digital Costas Loop (DCL) contains most of
the baseband processing functions needed to implement a
digital Costas Loop Demodulator. These functions include
LO generation/mixing, matched filtering, AGC, carrier phase
and frequency error detection, timing error detection, carrier
loop filtering, bit sync loop filtering, lock detection,
acquisition/tracking control, and soft decision slicing for
forward error correction algorithms. While the DCL is
designed to work with the HSP50110 Digital Quadrature
Tuner (DQT) as a variable rate PSK demodulator for satellite
demodulation, functions on the chip are common to many
communications receivers.
The DCL provides the processing blocks for the three
tracking loops commonly found in a data demodulator: the
Automatic Gain Control (AGC) loop, the Carrier Tracking
Loop, and a Symbol Tracking Loop. The AGC loop adjusts
for input signal power variations caused by path loss or
signal-to-noise variations. The carrier tracking loop removes
the frequency and phase uncertainties in the carrier due to
oscillator inaccuracies and doppler. The symbol tracking
loop removes the frequency and phase uncertainties in the
data and generates a recovered clock synchronous with the
received data. Each loop consists of an error detector, a loop
filter, and a frequency or gain adjustment/control. The AGC
loop is internal to the DCL, while the symbol and carrier
tracking loops are closed external to the DCL. When the
DCL is used together with the HSP50110, the tracking loops
are closed around the baseband filtering to center the signal
in the filter bandwidth. In addition, the AGC function is
divided between the two chips with the HSP50110 providing
the coarse AGC, and the HSP50210 providing the fine or
final AGC.
A top level block diagram of the HSP50210 is shown in
Figure 1. This diagram shows the major blocks and the
multiplexers used to reconfigure the data path for various
architectures.
If serial input mode is selected, the I and Q data enters via
the ISER and QSER pins using SERCLK and SSYNC. The
beginning of a serial word is designated by asserting
SSYNC ‘high’ one SERCLK prior to the first data bit, as
shown in Figure 2. On the following SERCLK’s, data is
shifted into the register until all 10 bits have been input. Data
shifting is then disabled and the contents of the register are
held until the next assertion of SSYNC. The assertion of a
SSYNC transfers data into the processing pipeline, and the
Shift Register is enabled to accept new data on the following
SERCLK. When data is transferred to the processing
pipeline by SSYNC, a processing enable is generated which
follows the data through the pipeline. This enable allows the
delay through processing elements (like the loop filters) to be
minimized since their pipeline delay is expressed in CLKs
not SSYNC periods.
Note: SSYNC should not be
asserted for more than one SERCLK cycle.
SERCLK
SSYNC
ISER/
QSER
SSYNC LEADS 1st DATA BIT
MSB
MSB
NOTE: Data must be loaded MSB first.
FIGURE 2. SERIAL INPUT TIMING FOR ISER AND QSER INPUTS
Input Level Detector
The Input Level Detector generates a one-bit error signal for
an external IF AGC filter and amplifier. The error signal is
generated by comparing the magnitude of the input samples
to a user programmable threshold. The HI/LO pin is then
driven “high” or “low” depending on the relationship of its
magnitude to the threshold. The sense of the HI/LO pin is
programmable so that a magnitude exceeding the threshold
can either be represented as a “high” or “low” logic state.
The Input Level Detector (HI/LO output) threshold and the
sense are set by the Data Path Configuration Control
Register bits 16-23 and 13 (see Table 14).
Note: The Input
Level Detector is typically not used in applications
which use the HSP50210 with the HSP50110.
The high/low outputs can be integrated by an external loop
filter to close an AGC loop. Using this method, the gain of
the loop forces the median magnitude of the input samples
to the threshold. When the magnitude of half of the samples
is above the threshold (and half is below), the error signal is
integrated to zero by the loop filter.
The magnitude of the complex input is estimated by:
Mag (I, Q)
=
I
+
0.375
×
Q if I
>
Q and
Mag (I, Q)
=
Q
+
0.375
×
I if Q
>
I
(EQ. 1)
Input Controller
In-Phase (I) and Quadrature (Q) data enters the part through
the Input Controller. The 10-bit data enters in either serial or
parallel fashion using either two’s complement or offset
binary format. The input mode and binary format is set in the
Data Path Configuration Control Register, bits 14 and 15
(see Table 14).
If Parallel Input mode is selected, I and Q data are clocked
into the part through IIN0-9 and QIN0-9 respectively. Data
enters the processing pipeline when the input enable
(SYNC) is sampled “low” by the processing clock (CLK). The
enable signal is pipelined with the data to the various
processing elements to minimize pipeline delay where
possible. As a result, the pipeline delay through the AGC,
Carrier Tracking, and Symbol Tracking Loop Filters is
measured in CLKs; not input data samples.
3-257
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
