HSP48212
Data Sheet
May 1999
File Number
3627.2
Digital Video Mixer
The Intersil HSP48212 is a 68 pin Digital Video Mixer IC
intended for use in multimedia and medical imaging
applications.
The HSP48212 allows the user to mix two video sources
based on a programmable weighting factor. After weighting
the input data signals, the Video Mixer simply adds the two
weighted signals mathematically. This results in the mixed
output, which is a weighted sum of the two sources.
The input and output interfaces are synchronous with respect
to the input clock, simplifying the user interface requirements.
Input Data (DINA, DINB), Mix Factor (M) and control signals
(RND, TCB) may be delayed relative to each other in order to
compensate for any misalignment that may have occurred
prior to entering the HSP48212. Each input’s delay may be
independently programmed up to seven clock cycles.
The output data may be rounded to 8, 10, 12, or 13-bits. The
enabling of data onto the output data bus is under the user’s
control via an output enable signal (OE).
Features
• 12-Bit Pixel Data
• Two’s Complement or Unsigned Data
• 12-Bit Mix Factor
• 13-Bit Signed or Unsigned Three State Output
• Overflow Detection and Output Saturation
• Rounding to 8, 10, 12, or 13-Bits
• Input and Output Pixel Data Synchronous to Clock
• Programmable Pipeline Delay of up to 7 Clock Cycles for
Control of Misaligned Input Data
• TTL Compatible Inputs/Outputs
• DC to 40MHz Clock Rate
Applications
• Video Summing (Frame Addition)
• Video Mixing
• Fade In/Out
• Video Switching
Ordering Information
PART NUMBER
HSP48212VC-40
HSP48212JC-40
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
PACKAGE
64 Ld MQFP
68 Ld PLCC
PKG. NO.
Q64.14x14
N68.95
• High Speed Multiplying
Block Diagram
TCB
DELAY
0-7
DINB0-11
12
DELAY
0-7
RND0-1
2
DELAY
0-7
1-M
DELAY
0-7
SHIFT
LEFT
FORMAT
OUTPUT
M
12
Σ
DOUT0-12
13
DINA0-11
12
DELAY
0-7
OE
DOUT = 2 x [DINA x M + DINB x (1-M)]
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HSP48212
Pin Descriptions
NAME
CLK
DINA0-11
PLCC PIN
9
29-31
33-34
36-38
40-43
10-15, 17
19-23
62-65
67-68
2-7
28
TYPE
I
I
DESCRIPTION
Clock Input. All signal pins are synchronous with respect to this clock except LD, DEL, OE, and BY-
PASS.
Input Data Bus. Provides data to the Mixer from one video source. Synchronous to the rising edge
of CLK.
DINB0-11
M0-11
I
I
Input Data Bus. Provides data to the Mixer from one video source. Synchronous to the rising edge
of CLK.
Mix Input Bus. The range of M is from 0 to 1. The number format is unsigned, with one bit position
to the left of the binary point. If a value greater than 1 is placed on this bus, the internal circuitry will
saturate M to 1, i.e, anytime the MSB is 1, the internal value defaults to 1.00000000000; synchro-
nous to the rising edge of CLK.
Specifies the number format of the input data busses DINA and DINB. 1 = unsigned, 0 = 2’s com-
plement. The signal has the same number of latency stages as the incoming data. Therefore, the
number format affects the incoming data but not the data in the internal pipeline stages. Synchro-
nous to the rising edge of CLK.
Specifies the number of significant bits on the output bus. 00 = 8-bit, 01 = 10-bit,
10 = 12-bit, 11 = 13-bit. Rounding is performed by adding a binary 1 to the bit position to the right of
the desired LSB. The remaining bits are forced to zero. These control signals have the same number
of latency stages as the incoming data. Therefore, the output round format does not take effect until
the current data has propagated to the output. Synchronous to the rising edge of CLK.
Mix Enable. This pin is used to disable the clock signal which samples the Mix input. When MIXEN
= 1, the M0-11 bus is sampled by the rising edge of CLK. When MIXEN = 0, the M0-11 bus is ignored
and the previously stored value of M0-11 is used. Synchronous to the rising edge of CLK.
Asynchronous Load Pin. LD is used to load the delay control registers. The delay control word is
loaded serially from LSB to MSB. This signal drives the clock input to a
15-bit serial shift register. Each LD cycle, the data is transferred through the register bank on the
rising edge of LD In order to load the delay control word, the user must supply exactly 15 LD pulses.
Delay Input. This is the serial input data that is sampled by the rising edge of LD. It is the input to the
first stage of the 15-bit serial shift register which contains the delay control word. Synchronous to the
rising edge of LD.
Allows user to disable (bypass) the LD interface and use the default delay paths. When BYPASS =
1, the delay control word is forced to all 0’s and no extra delays are included in the paths. When BY-
PASS = 0, the delay control word must be initialized using the LD/DEL interface in order for the chip
to give predictable results. This pin is asynchronous and is not intended to change states during op-
eration.
Output Data Bus. The data on this bus reflects the results of the equation:
2x[AxM + Bx(1-M)]. The number format of the output is either 2’s complement or unsigned depend-
ing on the value of the TC signal during data input. The representation of DOUT is also dependent
on the value sampled on RND0-1 during data input.
(See RND0-1 and TC pin description).
Output Enable. Asynchronous input which takes effect immediately following a transition. When OE =
0 the DOUT bus is driving, when OE = 1 the DOUT bus is not driven (floating).
5V power supply. There are 3 V
CC
pads.
0V power supply. There are 3 GND pads.
TC
I
RND0-1
24-25
I
MIXEN
8
I
LD
27
I
DEL
26
I
BYPASS
61
I
DOUT0-12
59-56
54-53
51-50
48-44
60
32, 49, 66
16, 39, 55
O
OE
V
CC
GND
I
I
I
3
HSP48212
Functional Description
The Digital Video Mixer is intended for use in professional
video, multimedia and medical imaging applications. The
HSP48212 allows the user to mix two video sources based
on a programmable weighting factor. After weighting the
input data signals, the Video Mixer simply adds the two
weighted signals mathematically. This results in the mixed
output, which is a weighted sum of the two sources. The
fundamental equation implemented by this architecture is:
DOUT = 2 x
[
DINA x M + DINB x
(
1 -M
) ]
(EQ. 1)
Input Data Format
DINA0-11 and DINB0-11 represent two digital video sources
(pixels). Each input bus has 12-bits of precision. They may
be represented in two’s complement form (TC = 0) or in
unsigned form (TC = 1). It is important to note that DINA0-11
and DINB0-11 must be represented in the same format (i.e.,
no mixed mode operation is allowed).
M0-11 supplies the weighting (Mix) factor and has 12-bits of
precision. M0-11 must be represented in unsigned format and
may range from 0 to 1. If a value greater than 1 is placed on the
bus, the internal circuitry will saturate M0-11 to 1.00000000000.
DINA0-11, DINB0-11, and M0-11 are synchronously
registered on the rising edge of CLK.
The signal MIXEN allows the user to disable the internal
clock signal which samples the M0-11 input bus. When
MIXEN = 0, the M0-11 bus is ignored and the previously
sampled M0-11 value is used. When MIXEN = 1, the M0-11
bus is sampled on the rising edge of CLK.
where DINA and DINB are the two video sources (pixels)
and M is the weighting (Mix) factor. As expressed by this
equation, the output DOUT is a weighted average of the
incoming pixels. For instance, when M is set to 0 the DINB
input source is passed to the output, and when M is set to 1
the DINA input is passed to the output, and when M is set to
0.5 the output is the sum of the two sources DINA and DINB.
The user can therefore vary the mix factor to apply different
weights to each of the inputs DINA, DINB. This allows
functions such as fading in, fading out, fading between
images, graphics overlays, and keying. The multiplication
factor of 2 as seen in (EQ. 1) is accomplished through a 1-bit
shift left (See Figure 1). This shifter is not programmable and
cannot be accessed by the user.
The Functional Block Diagram is shown in Figure 1. It can be
seen that (EQ. 1) is directly implemented by this architecture.
The architecture has a 6 stage inherent latency. This
architecture is extremely flexible in that it allows the user to
account for misaligned input data by independently
programming up to seven additional delay stages for DINA0-
11, DINB0-11, and M0-11, as well as for the format control
signals TC and RND0-1. The programmable delay registers
are controlled by the signals DEL, LD, and BYPASS.
The HSP48212 input interface is primarily synchronous to the
rising edge of CLK with the exception of the programmable
delay control signals DEL, LD, and BYPASS. The output data
bus DOUT0-12 is registered synchronous to the rising edge of
CLK and may also be controlled via the asynchronous output
enable signal OE. The input data, DINA0-11 and DINB0-11,
as well as the mix factor M0-11 have 12-bit precision. The
output data DOUT0-12 has 13-bit precision to allow for 1-bit of
growth.
The signals TC and RND0-1 control the format of the input
and output data. TC allows DINA0-11 and DINB 0-11 to be
either two’s complement or unsigned (Note: DINA0-11 and
DINB0-11 must have the same format, i.e., no mixed mode).
The output data DOUT0-12 can be rounded to 8, 10, 12, or
13-bits as determined by the control signals RND0-1.
Programmable Delay
The input data (DINA0-11, DINB0-11), mix factor (M0-11),
and control signals (RND0-1, TC), may be delayed relative to
each other in order to compensate for any misalignment that
may have occurred prior to entering the HSP48212. Each
input’s delay may be independently programmed for up to
seven delays. In other words, the user can program a
different number of pipeline delays for each input. This
programmed delay is in addition to the inherent 6 stage
delay required by the architecture.
As shown in Figures 2 and 3, the programmable delay
information is loaded using the signals LD and DEL. LD is
the asynchronous load pin used to clock in the delay control
word. The delay control word is clocked into a 15-bit serial
shift register on the rising edge of LD (i.e., DEL is
synchronous to LD). The delay control word data is supplied
by the DEL signal beginning with the least significant bit and
continuing until the most significant bit has been clocked in.
On each LD cycle the DEL data input is transferred through
the register bank. The user must supply exactly 15 LD
pulses; if the shift register is clocked more than 15 times,
only the most recent 15 data inputs will be stored.
As previously stated, the length of the control word is 15-bits: 3-
bits are allocated for each of the 5 inputs, DINA0-11, DINB0-11,
M0-11, RND0-1, and TC. Each 3-bits of the control word allow
the user to specify from 0 to 7 additional delay stages by
programming the binary equivalent of the desired delay into the
appropriate bit position of the delay control word register (e.g.,
000 for 0 delays, 001 for 1 delay, ..., 111 for 7 delays).
5
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
