HSP45116
Data Sheet
May 1999
File Number
2485.7
Numerically Controlled
Oscillator/Modulator
The Intersil HSP45116 combines a high performance
quadrature Numerically Controlled Oscillator (NCO) and a
high speed 16-bit Complex Multiplier/Accumulator (CMAC)
on a single IC. This combination of functions allows a
complex vector to be multiplied by the internally generated
(cos, sin) vector for quadrature modulation and
demodulation. As shown in the Block Diagram, the
HSP45116 is divided into three main sections. The
Phase/Frequency Control Section (PFCS) and the
Sine/Cosine Section together form a complex NCO. The
CMAC multiplies the output of the Sine/ Cosine Section with
an external complex vector.
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.008Hz at 33MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC
multiplies this (cos, sin) vector by an external complex vector
and can accumulate the result. The resulting complex vectors
are available through two 20-bit output ports which maintain
the 90dB spectral purity. This result can be accumulated
internally to implement an accumulate and dump filter.
A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be down converted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal.
Features
• NCO and CMAC on One Chip
• 15MHz, 25.6MHz, 33MHz Versions
• 32-Bit Frequency Control
• 16-Bit Phase Modulation
• 16-Bit CMAC
• 0.008Hz Tuning Resolution at 33MHz
• Spurious Frequency Components < -90dBc
• Fully Static CMOS
Applications
• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL
• Phase Shifter
• Polar to Cartesian Conversions
Ordering Information
PART NUMBER
HSP45116VC-15
HSP45116VC-25
HSP45116GC-15
HSP45116GC-25
HSP45116GC-33
HSP45116GI-15
HSP45116GI-25
HSP45116GI-33
HSP45116GM-15/883
HSP45116GM-25/883
HSP45116AVC-52
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
-55 to 125
-55 to 125
0 to 70
PACKAGE
PKG. NO.
160 Ld MQFP Q160.28x28
160 Ld MQFP Q160.28x28
145 Ld CPGA G145.A
145 Ld CPGA G145.A
145 Ld CPGA G145.A
145 Ld CPGA G145.A
145 Ld CPGA G145.A
145 Ld CPGA G145.A
145 Ld CPGA G145.A
145 Ld CPGA G145.A
160 Ld MQFP Q160.28x28
†
This part has its own data sheet under HSP45116A, AnswerFAX
document no. 4156.
Block Diagram
VECTOR INPUT
R
I
SINE/
COSINE
ARGUMENT
MICROPROCESSOR
INTERFACE
INDIVIDUAL
CONTROL SIGNALS
PHASE/
FREQUENCY
CONTROL
SECTION
SIN
SINE/
COSINE
SECTION
COS
CMAC
R
I
VECTOR OUTPUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
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Copyright
©
Intersil Corporation 1999
HSP45116
Pin Description
NAME
V
CC
GND
C0-15
AD0-1
CS
WR
CLK
ENPHREG
ENOFREG
ENCFREG
ENPHAC
ENTIREG
NUMBER
A1, A9, A15, G1,
J15, Q1, Q7, Q15
A8, A14, B1, H1,
H15, P15, Q2, Q8
N8-11, P8-13,
Q9-14
N7, P7
P6
Q6
Q5
M1
N1
N5
Q3
P5
TYPE
-
-
I
I
I
I
I
I
I
I
I
I
+5V Power supply input.
Power supply ground input.
Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB.
Address pins for selecting destination of C0-15 data.
Chip Select (active low).
Write Enable. Data is clocked into the register selected by AD0-1 on the rising edge of WR when
the CS line is low.
Clock. All registers, except the control registers clocked with WR, are clocked (when enabled)
by the rising edge of CLK.
Phase Register Enable (active low). Registered on chip by CLK. When active, after being
clocked onto chip, ENPHREG enables the clocking of data into the phase register.
Frequency Offset Register Enable (active Low). Registered on chip by CLK. When active, after
being clocked onto chip, ENOFREG enables clocking of data into the frequency offset register.
Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENCFREG enables clocking of data into the center frequency register.
Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENPHAC enables clocking of the phase accumulator register.
Time Interval Control Register Enable (active low). Registered on chip by CLK. When active,
after being clocked onto chip, ENTIREG enables clocking of data into the time accumulator
register.
Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by
CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and
imaginary input data register.
Modulo
π/2π
Select. When low, the Sine and Cosine ROMs are addressed modulo 2π (360
degrees). When high, the most significant address bit is held low so that the ROMs are
addressed modulo
π
(180 degrees). This input is registered on chip by clock.
Frequency Offset Register Output Zero (active low). Registered on chip by CLK. When active,
after being clocked onto chip, CLROFR zeros the data path from the frequency offset register to
the frequency adder. New data can still be clocked into the frequency offset register; CLROFR
does not affect the contents of the register.
Phase Accumulator Load Control (active low). Registered on chip by CLK. Zeroes feedback path
in the phase accumulator without clearing the phase accumulator register.
External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90,
180, or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of
the phase control path are set to zero.
These bits are loaded into the phase register when ENPHREG is low.
PMSEL
P3
I
Phase Modulation Select Line. This line determines the source of the data clocked into the phase
register. When high, the phase control register is selected. When low, the external modulation pins
(MOD0-1) are selected for the most significant two bits and the least significant two bits and the
least significant 14 bits are set to zero. This control is registered by CLK.
ROM Bypass, Timer Load. Active low, registered by CLK. This input bypasses the sine/ cosine
ROM so that the 16-bit phase adder output and lower 16 bits of the phase accumulator go
directly to the CMAC’s sine and cosine inputs, respectively. It also enables loading of the timer
accumulator register by zeroing the feedback in the accumulator.
Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to
increment by one, in addition to the values in the phase accumulator register and frequency
adder.
DESCRIPTION
ENI
Q4
I
MODPI/2PI
N6
I
CLROFR
P4
I
LOAD
MOD0-1
N4
M3, N3
I
I
RBYTILD
L3
I
PACI
P2
I
5
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