CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
Logical One Input
Voltage
Logical Zero Input
Voltage
Logical One Input
Voltage Clock
Logical Zero Input
Voltage Clock
Output HIGH Voltage
SYMBOL
V
IH
V
IL
TEST
CONDITIONS
V
CC
= 5.5V
V
CC
= 4.5V
GROUP A
SUBGROUPS
1, 2, 3
TEMPERATURE (
o
C)
55
≤
T
A
≤
125
55
≤
T
A
≤
125
55
≤
T
A
≤
125
55
≤
T
A
≤
125
55
≤
T
A
≤
125
55
≤
T
A
≤
125
55
≤
T
A
≤
125
55
≤
T
A
≤
125
55
≤
T
A
≤
125
55
≤
T
A
≤
125
MIN
2.2
MAX
-
UNITS
V
1, 2, 3
-
0.8
V
V
IHC
V
CC
= 5.5V
1, 2, 3
3.0
-
V
V
ILC
V
CC
= 4.5V
1, 2, 3
-
0.8
V
V
OH
V
OL
I
I
I
O
I
OH
= -400µA
V
CC
= 4.5V (Note 2)
I
OL
= +2.0mA
V
CC
= 4.5V (Note 2)
V
IN
= V
CC
or GND V
CC
= 5.5V
V
OUT
= V
CC
or GND
V
CC
= 5.5V
V
IN
= V
CC
or GND, V
CC
= 5.5V, (Note 5)
f = 15MHz,
V
IN
= V
CC
or GND
V
CC
= 5.5V
(Notes 3, 5)
(Note 4)
1, 2, 3
2.6
-
V
Output LOW Voltage
1, 2, 3
-
0.4
V
µA
µA
µA
Input Leakage Current
1, 2, 3
-10
+10
Output or I/O Leakage
Current
Standby Power Supply
Current
Operating Power Supply
Current
1, 2, 3
-10
+10
I
CCSB
1, 2, 3
-
500
I
CCOP
1, 2, 3
-
150
mA
Functional Test
NOTES:
FT
7, 8
55
≤
T
A
≤
125
-
-
2. Interchanging of force and sense conditions is permitted.
3. Operating Supply Current is proportional to frequency, typical rating is 10mA/MHz.
4. Tested as follows: f = 1MHz, V
IH
(clock inputs) = 3.4V, V
IH
(all other inputs) = 2.6V, V
IL
= 0.4V, V
OH
≥
1.5V, and V
OL
≤
1.5V.
5. Output per test load circuit with switch open and C
= 4.5V and 5.5V. Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 3.0V and 0V; timing
reference levels (CLK) 2.0V; all others 1.5V. Output load per test load circuit with switch closed and C
L
= 40pF. Output transition is measured
at V
OH
≥
1.5V and V
OL
≤
1.5V.
7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG, or ENTIREG is active.
8. Transition is measured at
±200mV
from steady state voltage, output loading per test load circuit, with switch closed and C
L
= 40pF.
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
TEMPERATURE
(
o
C)
T
A
- +25
-15
MIN
-
MAX
15
MIN
-
-25
MAX
15
UNITS
pF
SYMBOL
t
DEO
t
PO
t
TO
t
OE
(Note 8)
NOTES
GROUP A
SUBGROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
TEMPERATURE
(
o
C)
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
MIN
40
-
-
-
MAX
-
30
30
25
-25 (25.6MHz)
MIN
27
-
-
-
MAX
-
20
20
20
UNITS
ns
ns
ns
ns
t
MD
9, 10, 11
-
40
-
28
ns
PARAMETER
Input Capacitance
SYMBOL
C
IN
TEST CONDITIONS
V
CC
= Open, f = 1MHz All
measurements are refer-
enced to device GND
NOTES
9
Output Capacitance
Output Disable Time
Output Rise Time
Output Fall Time
NOTES:
C
OUT
t
OD
t
R
t
F
From 0.8V to 2.0V
From 2.0V to 0.8V
9
9, 10
9, 10
9, 10
T
A
- +25
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-
-
-
-
15
20
8
8
-
-
-
-
15
15
8
8
pF
ns
ns
ns
9. The parameters in Table 3 are controlled via design or process parameters and not directly tested. Characterized upon initial design and after
major process and/or design changes.
10. Loading is as specified in the test load circuit with C
L
= 40pF.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Tess
Interim Test
PDA
Final Test
Group A
Groups C & D
METHOD
100%/5004
100%/5004
100%
100%
-
Samples
SUBGROUPS
-
-
1
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
4
HSP45116/883
Burn-In Circuit
145 PIN PGA
TOP VIEW
1
A
V
CC
2
IMIN4
3
IMIN8
4
IMIN9
5
6
7
8
GND
9
V
CC
10
IO18
11
IO15
12
IO12
13
IO10
14
GND
15
V
CC
A
IMIN11 IMIN15 IMIN16
B
GND
IMIN 1
IMIN5
IMIN7
IMIN10 IMIN13 IMIN14
IO19
IO16
IO14
IO11
IO8
IO7
IO5
IO2
B
C
RIN15
RIN18
IMIN2
IMIN3
IMIN6
IMIN12 IMIN17 IMIN18
IO17
IO13
IO9
IO6
IO4
IO1
RO18
C
D
RIN13
RIN17
IMIN0
INDEX
IO3
RO19
RO17
D
E
RIN10
RIN14
RIN16
IO0
RO16
RO15
E
F
RIN7
RIN11
RIN12
RO14
RO13
RO11
F
G
V
CC
RIN9
RIN8
RO9
RO12
RO10
G
H
GND
RIN6
RIN5
RO8
RO7
GND
H
J
RIN3
RIN1
RIN4
RO5
RO4
V
CC
J
K
RIN2
RIN0
SH1
RO1
RO2
RO6
K
L
SH0
ENPH
REG
ACC
RBYTILD
PACO
DET1
RO3
L
M
PEAK
MOD1
ENCF
REG
MODPI
/2PI
CS
OUT-
MUX1
OEREXT
OEI
RO0
M
N
ENOF
REG BINFMT MOD0
LOAD
AD0
C14
C13
C8
C2
OUT-
MUX0
OEIEXT
DET0
N
P
TICO
PACI
PMSEL
CLROFR ENTIREG
AD1
C15
C10
C9
C6
C3
C1
OER
GND
P
Q
V
CC
1
GND
2
ENPHAC
ENI
4
CLK
5
WR
6
V
CC
7
GND
8
C12
9
C11
10
C7
11
C5
12
C4
13
C0
14
V
CC
15
Q
3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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