CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
Logical One Input Voltage
Logical Zero Input Voltage
Output HlGH Voltage
SYMBOL
V
lH
V
IL
V
OH
V
OL
I
I
I
O
V
IHC
V
ILC
I
CCSB
I
CCOP
FT
TEST CONDITIONS
V
CC
= 5.5V
V
CC
= 4.5V
I
OH
= -400µA
V
CC
= 4.5V (Note 2)
I
OL
= +2.0mA
V
CC
= 4.5V (Note 2)
V
IN
= V
CC
or GND
V
CC
= 5.5V
V
OUT
= V
CC
or GND
V
CC
= 5.5V
V
CC
= 5.5V
V
CC
= 4.5V
V
IN
= V
CC
or GND
V
CC
= 5.5V, (Note 5)
f = 25.6MHz
V
CC
= 5.5V (Notes 3, 5)
(Note 4)
GROUP A
SUBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
TEMPERATURE
(
o
C)
55
≤
T
A
≤
+125
55
≤
T
A
≤
+125
55
≤
T
A
≤
+125
55
≤
T
A
≤
+125
55
≤
T
A
≤
+125
55
≤
T
A
≤
+125
55
≤
T
A
≤
+125
55
≤
T
A
≤
+125
55
≤
T
A
≤
+125
55
≤
T
A
≤
+125
55
≤
T
A
≤
+125
MIN
2.2
-
2.6
MAX
-
0.8
-
UNITS
V
V
V
Output LOW Voltage
1, 2, 3
-
0.4
V
µA
µA
Input Leakage Current
1, 2, 3
-10
+10
Output Leakage Current
1, 2, 3
-10
+10
Clock lnput High
Clock Input Low
Standby Power Supply
Current
Operating Power Supply Cur-
rent
Functional Test
NOTES:
1, 2, 3
1, 2, 3
1, 2, 3
3.0
-
-
-
0.8
500
V
V
µA
1, 2, 3
-
205
mA
7, 8
-
-
-
2. Interchanging of force and sense conditions is permitted.
3. Operating supply current is proportional to frequency, typical rating is 8mA/MHz.
4. Tested as follows: f = 1MHz, V
IH
= 2.6, V
IL
= 0.4, V
OH
≥
1.5V, V
OL
≤
1.5V, V
IHC
= 3.4V, and V
ILC
= 0.4V.
5. Loading is as specified in the test load circuit with C
L
= 40pF.
2
HSP45106/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
-25 (25.6MHz)
PARAMETER
CLK Period
CLK High
CLK Low
WR Period
WR High
WR Low
Setup Time A(2:0), CS to WR
Going High
Hold Time A(2:0), CS from WR Go-
ing High
Setup Time C(15:0) to WR
Going High
Hold Time C(15:0) from WR
Going High
Setup Time WR High to CLK High
Setup Time MOD(2:0) to CLK
Going High
Hold Time MOD(2:0) from CLK Go-
ing High
Setup Time ENPOREG,
ENOFREG, ENCFREG,
ENPHAC, ENTIREG, INHOFR,
PMSEL, INITPAC, BINFMT, TEST,
PAR/SER, PACI, INITTAC to CLK
Going High
Setup Time ENPOREG,
ENOFREG, ENCFREG,
ENPHAC, ENTIREG, INHOFR,
PMSEL, INITPAC, BINFMT, TEST,
PAR/SER, PACI, INITTAC from
CLK Going High
CLK to Output Delay SIN(15:0),
COS(15:0), TICO
CLK to Output Delay DACSTRB
Output Enable Time
NOTES:
6. AC Testing: V
CC
= 4.5V and 5.5V. Inputs are driven at 3.0V for Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are
made at 1.5V for both a Logic “1” and 0”. CLK is driven at 4.0V and 0V and measured at 2.0V. Output load per test load circuit with switch closed
and C
L
= 40pF.
7. Transition is measured at
±200mV
from steady state voltage with loading as specified by test load circuit and C
L
= 40pF.
8. If ENOFRCTL, ENCFRACTL, ENTICTL, or ENPHREG are active, care must be taken to not violate setup and hold times to these registers when
writing data into the chip via the C(15:0) port.
SYMBOL
t
CP
t
CH
t
CL
t
WP
t
WH
t
WL
t
AWS
t
AWH
t
CWS
t
CWH
t
WC
t
MCS
t
MCH
t
ECS
Note 8
NOTES
GROUP A
SUBGROUP
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
TEMPERATURE
(
o
C)
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
MIN
39
15
15
39
15
15
13
MAX
-
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
9, 10, 11
2
-
ns
9, 10, 11
15
-
ns
9, 10, 11
1
-
ns
9, 10, 11
9, 10, 11
16
15
-
-
ns
ns
9, 10, 11
1
-
ns
9, 10, 11
12
-
ns
t
ECH
9, 10, 11
-55
≤
T
A
≤
125
1
-
ns
t
DO
t
DSO
t
OE
Note 7
9, 10, 11
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-
18
ns
9, 10, 11
9, 10, 11
2
-
18
12
ns
ns
3
HSP45106/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
-25 (25MHz)
PARAMETER
Input Capacitance
SYMBOL
C
IN
CONDITIONS
V
CC
= Open, f = 1MHz, all measure-
ments are referenced to device GND.
V
CC
= Open, f = 1MHz, all measure-
ments are referenced to device GND.
NOTES
9
TEMPERATURE
(
o
C)
T
A
= 25
T
A
= 25
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
MIN
-
MAX
10
UNITS
pF
Output Capacitance
C
OUT
t
OEZ
t
OR
t
OF
9
-
10
pF
Output Disable Delay
Output Rise Time
Output Fall Time
NOTES:
9, 10
From 0.8V to 2.0V
From 20.V to 0.8V
9, 10
9, 10
-
-
-
15
8
8
ns
ns
ns
9. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.
10. Loading is as specified in the test load circuit with switch closed and C
L
= 40pF.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
CONFORMANCE GROUPS
Initial Test
Interim Test
PDA
Final Test
Group A
Groups C and D
METHOD
100%/5004
100%/5004
100%
100%
-
Samples/5005
SUBGROUPS
-
-
1
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
4
HSP45106/883
Burn-In Circuit
HSP45106/833 (PGA)
11
L
K
J
H
G
F
E
D
C
B
A
GND
FMT
INIPAC
ENP
HAC
ENTI
REG
ENCF
REG
CS
V
CC
10
SIN0
V
CC
PAR/
SEL
PACI
INITT
AC
ENPO
REG
GND
TEST
C10
A1
GND
C15
C14
C12
C11
C9
C13
C8
C6
V
CC
C7
C4
C5
INHOF
R
ENOF
REG
WR
COS6
COS7
9
SIN1
CLK
8
SIN3
SIN2
7
SIN5
V
CC
SIN6
6
SIN4
SIN8
SIN7
5
SIN9
SIN10
SIN11
4
SIN12
GND
3
SIN13
SIN15
2
SIN14
OES
OEC
COS2
COS4
COS8
1
DAC
STRB
COSO
COS1
COS3
COS5
V
CC
L
K
J
H
G
F
E
D
C
B
A PIN “A1”
COS11 COS10 COS9
GND
COS12
MOD2 MOD0
MOD1
PMSEL
A2
A0
INDEX
PIN COS15 COS13
C1
C3
TICO
C2
COS14
C0
PGA
PIN
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
NOTES:
PIN
NAME
C0
C2
C3
C5
C7
C8
C11
C14
GND
A0
PMSEL
COS14
TICO
C1
C4
V
CC
C13
C12
C15
A1
A2
BURN-IN
SIGNAL
F7
F7
F7
F8
F8
F10
F10
F11
GND
F8
F14
V
CC
/2
V
CC
/2
F7
F8
V
CC
F11
F11
F11
F7
F10
PGA
PIN
B11
C1
C2
C5
C6
C7
C10
C11
D1
D2
D10
D11
E1
E2
E3
E9
E10
E11
F1
F2
F3
PIN
NAME
MOD1
COS13
COS15
C6
C9
C10
MOD0
MOD2
COS12
GND
TEST
V
CC
COS9
COS10
COS11
WR
GND
CS
V
CC
COS8
COS7
BURN-IN
SIGNAL
F13
V
CC
/2
V
CC
/2
F8
F10
F10
F12
F14
V
CC
/2
GND
F14
V
CC
V
CC
/2
V
CC
/2
V
CC
/2
F4
GND
F6
V
CC
V
CC
/2
V
CC
/2
PGA
PIN
F9
F10
F11
G1
G2
G3
G9
G10
G11
H1
H2
H10
H11
J1
J2
J5
J6
J7
J10
J11
K1
PIN
NAME
ENOFREG
ENPOREG
ENCFREQ
COS5
COS4
COS6
INHOFR
INITTAC
ENTIREG
COS3
COS2
PACI
ENPHAC
COS1
OEC
SIN11
SIN7
SIN6
PAR/SER
INITPAC
COS0
BURN-IN
SIGNAL
F8
F4
F7
V
CC
/2
V
CC
/2
V
CC
/2
F11
F13
F12
V
CC
/2
V
CC
/2
F11
F10
V
CC
/2
F14
V
CC
/2
V
CC
/2
V
CC
/2
F13
F12
V
CC
/2
PGA
PIN
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
PIN
NAME
OES
SIN15
GND
SIN10
SIN8
V
CC
SIN2
CLK
V
CC
BINFMT
DACSTRB
SIN14
SIN13
SIN12
SIN9
SIN4
SIN5
SIN3
SIN1
SIN0
GND
BURN-IN
SIGNAL
F14
V
CC
/2
GND
V
CC
/2
V
CC
/2
V
CC
V
CC
/2
F0
V
CC
F6
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
GND
11. V
CC
/2 (2.7V
±10%)
used for outputs only.
12. 47kΩ (±20%) resistor connected to all pins except V
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