HSP43891
Data Sheet
May 1999
File Number
2785.5
Digital Filter
The HSP43891 is a video-speed Digital Filter (DF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells
cascaded internally and a shift and add output stage, all in
a single integrated circuit. Each filter cell contains a 9x9
two’s complement multiplier, three decimation registers and
a 26-bit accumulator. The output stage contains an
additional 26-bit accumulator which can add the contents of
any filter cell accumulator to the output stage accumulator
shifted right by 8-bits. The HSP43891 has a maximum
sample rate of 30MHz. The effective multiply-accumulate
(mac) rate is 240MHz.
The HSP43891 DF can be configured to process expanded
coefficient and word sizes. Multiple DFs can be cascaded
for larger filter lengths without degrading the sample rate or
a single DF can process larger filter lengths at less than
30MHz with multiple passes. The architecture permits
processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter
coefficients are less than 1.0, making even larger filter
lengths possible. The DF provides for 8-bit unsigned or
9-bit two’s complement arithmetic, independently
selectable for coefficients and signal data.
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
of
1
/
2
,
1
/
3
or
1
/
4
the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multiplication and NxN spatial
correlations/convolutions for image processing applications.
Features
• Eight Filter Cells
• 0MHz to 30MHz Sample Rate
• 9-Bit Coefficients and Signal Data
• 26-Bit Accumulator per Stage
• Filter Lengths Over 1000 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1-D and 2-D FIR Filters
• Radar/Sonar
• Digital Video
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
- Sample Rate Converters
Ordering Information
PART NUMBER
HSP43891VC-20
HSP43891VC-25
HSP43891VC-30
HSP43891JC-20
HSP43891JC-25
HSP43891JC-30
HSP43891GC-20
HSP43891GC-25
HSP43891GC-30
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
PKG. NO.
100 Lead MQFP Q100.14x20
100 Lead MQFP Q100.14x20
100 Lead MQFP Q100.14x20
84 Lead PLCC
84 Lead PLCC
84 Lead PLCC
85 Pin CPGA
85 Pin CPGA
85 Pin CPGA
N84.1.15
N84.1.15
N84.1.15
G85.A
G85.A
G85.A
Block Diagram
V
CC
DIENB
CIENB
DCM0 - 1
ERASE
CIN0 - 8
RESET
CLK
ADRO - 2
5
V
SS
DIN0 - DIN8
9
9
5
DF
FILTER
CELL 0
5
3
26
9
DF
FILTER
CELL 1
26
9
DF
FILTER
CELL 2
26
9
DF
FILTER
CELL 3
26
9
DF
FILTER
CELL 4
26
9
DF
FILTER
CELL 5
26
9
DF
FILTER
CELL 6
26
9
DF
FILTER 9
CELL 7
26
COUT0 - 8
COENB
MUX
RESET
CLK
SHADD
SENBL
SENBH
ADR0, ADR1, ADR2
2
26
OUTPUT
STAGE
2
SUM0 - 25
26
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HSP43891
Pinout
85 PIN GRID ARRAY (PGA)
1
A
B
2
3
4
5
6
DIN6
DIN1
7
DIN3
8
DIN0
9
CIN8
10
V
CC
CIN6
CIN5
CIN2
COUT2
11
V
SS
CIN4
CIN3
V
CC
L
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 V
CC
SUM13 V
SS
SUM11 SUM9
DIN2 CIENB CIN7
DIN4
K
SENBH SUM24 V
SS
DIENB DIN5
J
V
CC
SUM25
H
ADR1 ADR0
G
ADR2 DCM0
F
V
SS
COUT0 SHADD
E
COUT1 V
SS
COUT2
D
COUT3 COUT4
C
B
K SENBH SUM24
V
SS
V
CC
SUM19
V
SS
SUM15 SUM12 SUM10 SUM8 SUM6
A
V
SS
COENB V
CC
RESET DIN7
DIN6
DIN3
DIN0
CIN8
V
CC
V
SS
COUT5COUT6 ALIGN
PIN
DIENB DIN5
DIN4
CIN5
CIN3
CIN2
V
CC
CIN1
CIN0 SENBL
CLK
SUM5 SUM4
SUM20 SUM17 SUM16
SUM7
V
SS
V
CC
SUM19
V
SS
SUM15 SUM12 SUM10 SUM8 SUM6
1
2
3
4
5
6
7
8
9
10
11
V
SS
COENB V
CC
RESET DIN7
V
CC
COUT7 COUT8 ERASE DIN8
ALIGN
C COUT5 COUT6 PIN
D COUT3 COUT4
E COUT1
V
SS
V
SS
CIN1
CIN0 SENBL
V
CC
V
SS
HSP43891
F
G
H
J
COUT0 SHADD
CLK
ADR2 DCM0
ADR1 ADR0
V
CC
SUM25
SUM20 SUM17 SUM16
HSP43891
BOTTOM VIEW
PINS UP
SUM1 SUM3 SUM2
SUM0
V
CC
V
SS
TOP VIEW
PINS DOWN
SUM0
SUM1 SUM3 SUM2
SUM5 SUM4
SUM7
V
SS
V
CC
COUT7 COUT8 ERASE DIN8
DIN1
DIN2 CIENB CIN7
CIN6
CIN4
L
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14
V
CC
SUM13
V
SS
SUM11 SUM9
84 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)
V
SS
SUM24
DCM1
SUM25
SENBH
V
CC
ADDR0
ADDR1
V
SS
DCM0
ADDR2
CLK
SHADD
COUT0
COUT1
V
SS
COUT2
COUT3
COUT4
COUT5
V
CC
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
SUM23
SUM22
V
CC
SUM21
SUM20
SUM19
SUM18
V
SS
SUM17
SUM16
V
CC
SUM15
SUM14
SUM13
SUM12
V
SS
SUM11
SUM10
SUM9
SUM8
SUM7
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
COUT6
COUT7
V
SS
COUT8
COENB
V
CC
ERASE
RESET
DIENB
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
CIENB
CIN8
V
CC
HSP43891
TOP VIEW
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
SUM6
V
SS
SUM5
SUM4
V
CC
SUM3
SUM2
SUM1
SUM0
V
SS
SENBL
CIN0
CIN1
V
CC
CIN2
CIN3
CIN4
CIN5
V
SS
CIN6
CIN7
2
HSP43891
Pinout
(Continued)
100 LEAD MQFP
TOP VIEW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DCM1
SUM24
V
SS
V
SS
SUM23
SUM22
V
CC
V
CC
SUM21
SUM20
SUM19
SUM18
V
SS
V
SS
SUM17
SUM16
V
CC
V
CC
SUM15
SUM14
SUM13
SUM12
V
SS
SUM11
SUM10
SUM9
SUM8
SUM7
NC
SUM6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SUM5
SUM4
V
CC
SUM3
SUM2
SUM1
SUM0
V
SS
V
SS
SENBL
CIN0
CIN1
V
CC
CIN2
CIN3
CIN4
CIN5
V
SS
V
SS
V
SS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
COUT4
COUT5
V
CC
V
CC
COUT6
COUT7
V
SS
V
SS
COUT8
COENB
V
CC
V
CC
ERASE
RESET
DIENB
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
CIENB
CIN8
V
CC
CIN7
CIN6
V
SS
3
SENBH
V
CC
V
CC
ADDR0
ADDR1
V
SS
V
SS
DCM0
ADDR2
CLK
SHADD
V
CC
V
CC
COUT0
COUT1
V
SS
V
SS
COUT2
COUT3
SUM25
HSP43891
Pin Description
SYMBOL
V
CC
PIN
NUMBER
B1, J1, A3, K4,
L7, A10, F10,
D11
A1, F1, E2, K3,
K6, L9, A11,
F11, J11
G3
A5-8, B5-7, C6,
C7
I
I
TYPE
+5 power supply input.
NAME AND FUNCTION
V
SS
Power supply ground input.
CLK
DIN0-8
The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz.
These nine inputs are the data sample input bus. Nine-bit data samples are synchronously loaded
through these pins to the X register of each filter cell of the DF simultaneously. The DIENB signal en-
ables loading, which is synchronous on the rising edge of the clock signal.
The data samples can be either 9-bit two’s complement or 8-bit unsigned values. For 9-bit two’s com-
plement values, DIN8 is the sign bit. For 8-bit unsigned values, DIN8 must be held at logical zero.
DIENB
C5
I
A low on this input enables the data sample input bus (DIN0-8) to all the filter cells. A rising edge of the
CLK signal occurring while DIENB is low will load the X register of every filter cell with the 9-bit value
present on DIN0-8. A high on this input forces all the bits of the data sample input bus to zero; a rising
CLK edge when DIENB is high will load the X register of every filter cell with all zeros. This signal is
latched inside the device, delaying its effect by one clock internal to the device. Therefore it must be low
during the clock cycle immediately preceding presentation of the desired data on the DIN0-8 inputs. De-
tailed operation is shown in later timing diagrams.
These nine inputs are used to input the 9-bit coefficients. The coefficients are synchronously loaded
into the C register of filter CELL0 if a rising edge of CLK occurs while CIENB is low. The CIENB signal
is delayed by one clock as discussed below.
The coefficients can be either 9-bit two’s complement or 8-bit unsigned values. For 9-bit two’s comple-
ment values, CIN8 is the sign bit. For 8-bit unsigned values, CIN8 must be held at logical zero.
CIN0-8
A9, B9-11, C10,
C11, D10, E9,
E10
I
ALIGN PIN
CIENB
C3
B8
I
Used for aligning chip on socket or printed circuit board. This pin must be left as a no connect in circuit.
A low on this input enables the C register of every filter cell and the D (decimation) registers of every
filter cell according to the state of the DCM0-1 inputs. A rising edge of the CLK signal occurring while
CIENB is low will load the C register and appropriate D registers with the coefficient data present at
their inputs. This provides the mechanism for shifting coefficients from cell to cell through the device. A
high on this input freezes the contents of the C register and the D registers, ignoring the CLK signal.
This signal is latched and delayed by one clock internal to the DF. Therefore it must be low during the
clock cycle immediately preceding presentation of the desired coefficient on the CIN0-8 inputs. Detailed
operation is shown in later timing diagrams.
These nine three-state outputs are used to output the 9-bit coefficients from filter CELL7. These outputs
are enabled by the COENB signal low. These outputs may be tied to the CIN0-8 inputs of the same DF
to recirculate to coefficients, or they may be tied to the CIN0-8 inputs of another DF to cascade DFs for
longer filter lengths.
A low on the COENB input enables the COUT0-8 outputs. A high on this input places all these outputs
in their high impedance state.
These two inputs determine the use of the internal decimation registers as follows:
DCM1
0
0
1
1
DCM0
0
1
0
1
DECIMATION FUNCTION
Decimation registers not used
One decimation register is used
Two decimation registers are used
Three decimation registers are used
COUT0-8
B2, B3, C1, D1,
E1, C2, D2, F2,
E3
A2
L1, G2
O
COENB
DCM0-1
I
I
The coefficients pass from cell to cell at a rate determined by the number of decimation registers used.
When no decimation registers are used, coefficients move from cell to cell on each clock. When one
decimation register is used, coefficients move from cell to cell on every other clock, etc. These signals
are latched and delayed by one clock internal to the device.
4
HSP43891
Pin Description
SYMBOL
SUM0-25
(Continued)
TYPE
O
NAME AND FUNCTION
These 26 three-state outputs are used to output the results of the internal filter cell computations. Indi-
vidual filter cell results or the result of the shift and add output stage can be output. If an individual filter
cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD signal determines
whether the selected filter cell result or the output stage adder result is output. The signals SENBH and
SENBL enable the most significant and least significant bits of the SUM0-25 result respectively. Both
SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or larger bus. However
individual enables are provided to facilitate use with a 16-bit bus.
A low on this input enables result bits SUM16-25. A high on this input places these bits in their high
impedance state.
A low on this input enables result bits SUM0-15. A high on this input places these bits in their high im-
pedance state.
These three inputs select the one cell whose accumulator will be read through the output bus (SUM0-
25) or added to the output stage accumulator. They also determine which accumulator will be cleared
when ERASE is low. These inputs are latched in the DF and delayed by one clock internal to the device.
If ADR0-2 remains at the same address for more than one clock, the output at SUM0-25 will not change
to reflect any subsequent accumulator updates in the addressed cell. Only the result available during
the first clock, when ADR0-2 selects the cell, will be output. This does not hinder normal operation since
the ADR0-2 lines are changed sequentially. This feature facilitates the interface with slow memories
where the output is required to be fixed for more than one clock.
The SHADD input controls the activation of the shift and add operation in the output stage. This signal
is latched on chip and delayed by one clock internal to the device. Detailed explanation is given in the
DF Output Stage section.
A low on this input synchronously clears all the internal registers, except the cell accumulators It can
be used with ERASE to also clear all the accumulators simultaneously. This signal is latched in the DF
and delayed by one clock internal to the device.
A low on this input synchronously clears the cell accumulator selected by the ADR0-2 signals. If RESET
is also low simultaneously, all cell accumulators are cleared.
PIN
NUMBER
F9, G9-G11,
H10, H11, J2,
J5-J7, J10, K2,
K5, K7-K11,
L2-L6, L8, L10,
L11
K1
E11
G1, H1, H2
SENBH
SENBL
ADR0-2
I
I
I
SHADD
F3
I
RESET
A4
I
ERASE
B4
I
Functional Description
The Digital Filter Processor (DF) is composed of eight filter
cells cascaded together and an output stage for combining
or selecting filter cell outputs (See Block Diagram). Each
filter cell contains a multiplier-accumulator and several
registers (Figure 1). Each 9-bit coefficient is multiplied by a
9-bit data sample, with the result added to the 26-bit
accumulator contents. The coefficient output of each cell is
cascaded to the coefficient input of the next cell to its right.
DF Filter Cell
A 9-bit coefficient (CIN0-8) enters each cell through the C
register on the left and exits the cell on the right as signals
COUT0-8. With no decimation, the coefficient moves directly
from the C register to the output, and is valid on the clock
following its entrance. When decimation is selected the
coefficient exit is delayed by 1, 2 or 3 clocks by passing
through one or more decimation registers (D1, D2 or D3).
The combination of D registers through which the coefficient
passes is determined by the state of DCM0 and DCM1. The
output signals (COUT0-8) are connected to the CIN0-8
inputs of the next cell to its right. The COENB input signal
enables the COUT0-8 outputs of the right most cell to the
COUT0-8 pins of the device.
The C and D registers are enabled for loading by CIENB.
Loading is synchronous with CLK when CIENB is low. Note
that CIENB is latched internally. It enables the register for
loading after the next CLK following the onset of CIENB low.
Actual loading occurs on the second CLK following the onset
of CIENB low. Therefore CIENB must be low during the clock
cycle immediately preceding presentation of the coefficient
on the CIN0-8 inputs. In most basic FIR operations, CIENB
will be low throughout the process, so this latching and delay
sequence is only important during the initialization phase.
When CIENB is high, the coefficients are frozen.
The C and D registers are cleared synchronously under control
of RESET, which is latched and delayed exactly like CIENB.
The output of the C register (C0-8) is one input to 9 x 9
multiplier.
The other input to the 9 x 9 multiplier comes from the output
of the X register. This register is loaded with a data sample
from the device input signals DIN0-8 discussed above. The
X register is enabled for loading by DIENB. Loading is
synchronous with CLK when DIENB is low. Note that DIENB
is latched internally. It enables the register for loading after
the next CLK following the onset of DIENB low. Actual
loading occurs on the second CLK following the onset of
DIENB low; therefore, DIENB must be low during the clock
5
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