HSP43891/883
TM
Data Sheet
May 1999
FN2451.4
Digital Filter
The HSP43891/883 is a video-speed Digital Filter (DF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells cascaded
internally and a shift and add output stage, all in a single
integrated circuit. Each filter cell contains a 9 x 9 two’s
complement multiplier, three decimation registers and a 26-
bit accumulator. The output stage contains an additional 26-
bit accumulator which can add the contents of any filter cell
accumulator to the output stage accumulator shifted right by
8-bits. The HSP43891/883 has a maximum sample rate of
25.6MHz. The effective multiply-accumulate (mac) rate is
204MHz.
The HSP43891/883 DF can be configured to process
expanded coefficient and word sizes. Multiple DFs can be
cascaded for larger filter lengths without degrading the
sample rate or a single DF can process larger filter lengths
at less than 25.6MHz with multiple passes. The architecture
permits processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter coefficients
are less than 1.0, making even larger filter lengths possible.
The DF provides for 8-bit unsigned or 9-bit two’s
complement arithmetic, independently selectable for
coefficients and signal data.
Each DF filter cell contains three re-sampling or decimation
registers which permit output sample rate reduction at rates
of
1
/
2
,
1
/
3
or
1
/
4
the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multiplication and N x N spatial
correlations/convolutions for image processing applications.
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 0MHz to 25.6MHz Sample Rate
• Eight Filter Cells
• 9-Bit Coefficients and Signal Data
• Low Power CMOS Operation
- ICCSB = 500µA Maximum
- ICCOP = 160µA Maximum at 20MHz
• 26-Bit Accumulator per Stage
• Filter Lengths Up to 1032 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1-D and 2-D FIR Filters
• Radar/Sonar
• Digital Video
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
• Sample Rate Converter
Ordering Information
PART NUMBER
HSP43891GM-20/883
HSP43891GM-25/883
TEMP.
RANGE (
o
C)
-55 to 125
-55 to 125
PACKAGE
85 Ld PGA
85 Ld PGA
PKG.
NO.
G85.A
G85.A
Block Diagram
V
CC
DIENB
CIENB
DCM0 - 1
ERASE
CIN0 - 8
RESET
CLK
ADR0 - 2
RESET
CLK
SHADD
SENBL
SENBH
V
SS
DIN0 - DIN8
9
5
9
5
DF
FILTER
CELL 0
5
3
26
9
DF
FILTER
CELL 1
26
9
DF
FILTER
CELL 2
26
9
DF
FILTER
CELL 3
26
9
DF
FILTER
CELL 4
26
9
DF
FILTER
CELL 5
26
9
DF
FILTER
CELL 6
26
9
DF
FILTER 9
CELL 7
26
COUT0 - 8
COENB
MUX
ADR0, ADR1, ADR2
2
26
OUTPUT
STAGE
2
SUM0 - 25
26
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HSP43891/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V
Input/Output Voltage . . . . . . . . . . . . . . . . . GND -0.5V to V
CC
+0.5V
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
Ceramic PGA Package . . . . . . . . . . . .
36.0
7.0
Maximum Package Power Dissipation at 125
o
C
Ceramic PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.44W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Die Characteristics
Number of Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17,762
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Devices Guaranteed and 100% Tested
PARAMETER
Logical One Input Voltage
Logical Zero Input Voltage
Output HIGH Voltage
Output LOW Voltage
Input Leakage Current
Output Leakage Current
Clock Input High
Clock Input Low
Standby Power Supply
Current
Operating Power Supply
Current
Functional Test
NOTES:
2. Interchanging of force and sense conditions is permitted.
3. Operating Supply Current is proportional to frequency, typical rating is 8mA/MHz.
4. Tested as follows: f = 1MHz, V
IH
= 2.6, V
IL
= 0.4, V
OH
≥
1.5V, V
OL
≤
1.5V, V
IHC
= 3.4V, and V
ILC
= 0.4V.
SYMBOL
V
IH
V
IL
V
OH
V
OL
I
I
I
O
V
IHC
V
ILC
I
CCSB
CONDITIONS
V
CC
= 5.5V
V
CC
= 4.5V
I
OH
= 400µA
V
CC
= 4.5V (Note 2)
I
OL
= +2.0mA
V
CC
= 4.5V (Note 2)
V
IN
= V
CC
or GND
V
CC
= 5.5V
V
OUT
= V
CC
or GND
V
CC
= 5.5V
V
CC
= 5.5V
V
CC
= 4.5V
V
IN
= V
CC
or GND
V
CC
= 5.5V,
Outputs Open
f = 20.0MHz
V
CC
= 5.5V, (Note 3)
(Note 4)
GROUP A
SUBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
TEMPERATURE
(
o
C)
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
MIN
2.2
-
2.6
-
-10
-10
3.0
-
-
MAX
-
0.8
-
0.4
+10
+10
-
0.8
500
UNITS
V
V
V
V
µA
µA
V
V
µA
I
CCOP
FT
1, 2, 3
7, 8
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-
-
160.0
-
mA
4
HSP43891/883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
GROUP A
SUBGROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-20 (20MHz)
TEMP (
o
C)
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
MIN
50
20
20
20
0
-
-
-
MAX
-
-
-
-
-
24
20
31
-25 (25.6MHz)
MIN
39
16
16
17
0
-
-
-
MAX
-
ns
-
-
-
20
15
25
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
Clock Period
Clock Low
Clock High
Input Setup
Input Hold
CLK to Coefficient
Output Delay
Output Enable Delay
CLK to SUM Output
Delay
NOTE:
SYMBOL
t
CP
t
CL
t
CH
t
IS
t
IH
t
ODC
t
OED
t
ODS
NOTES
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
5. AC Testing: V
CC
= 4.5V and 5.5V. Inputs are driven at 3.0V for a Logic”1” and 0.0V for a Logic “0”. Input and output timing measurements are
made at 1.5V for both a Logic “1” and “0”. CLK is driven at 4.0V and 0V and measured at 2.0V.
TABLE 3. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
TEST
CONDITIONS
V
CC
= Open, f = 1MHz
All measurements are
referenced to device GND
-20 (20MHz)
NOTES
1
1
1, 2
1, 2
1, 2
TEMP (
o
C)
T
A
= 25
o
C
T
A
= 25
o
C
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
MIN
-
-
-
-
-
MAX
15
15
20
7
7
-25 (25.6MHz)
MIN
-
-
-
-
-
MAX
15
15
15
6
6
UNITS
pF
pF
ns
ns
ns
PARAMETER
Input Capacitance
Output Capacitance
Output Disable Delay
Output Rise Time
Output Fall Time
NOTES:
SYMBOL
C
IN
C
OUT
t
ODD
t
OR
t
OF
6. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design and after major process and/or design changes.
7. Loading is as specified in the test load circuit, C
L
= 40pF.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE
GROUPS
Initial Test
Interim Test
PDA
Final Test
Group A
Groups C and D
METHOD
100%/5004
100%/5004
100%
100%
-
Samples/5005
SUBGROUPS
-
-
1
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
5
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