CD40160BMS, CD40161BMS, CD40162BMS,
CD40163BMS
December 1992
File Number 3358
CMOS Synchronous Programmable 4-Bit
Counters
CD40160BMS,
CD40161BMS,
CD40162BMS
and
CD40163BMS are 4-bit synchronous programmable
counters. The CLEAR function of the CD40162BMS and
CD40163BMS is synchronous and a low level at the CLEAR
input sets all four outputs low on the next positive CLOCK
edge. The CLEAR function of the CD40160BMS and
CD40161BMS is asychronous and a low level at the CLEAR
input sets all four outputs low regardless of the state of the
CLOCK, LOAD, or ENABLE inputs. A low level at the LOAD
input disables the counter and causes the output to agree
with the setup data after the next CLOCK pulse regardless of
the conditions of the ENABLE inputs.
The carry look-ahead circuitry provides for cascading counters
for n-bit synchronous applications without additional gating.
Instrumental in accomplishing this function are two count-enable
inputs and a carry output (COUT). Counting is enabled when
both PE and TE inputs are high. The TE input is fed forward to
enable COUT. This enabled output produces a positive output
pulses with a duration approximately equal to the positive portion
of the Q1 output. This positive overflow carry pulse can be used
to enable successive cascaded stages. Logic transitions at the
PE or TE inputs may occur when the clock is either high or low.
The CD40160BMS through CD40163BMS types are functionally
equivalent to and pin-compatible with the TTL counter series
74LS160 through 74LS163 respectively.
The CD40160BMS, CD40161BMS, CD40162BMS and
CD40163BMS are supplied in these 16 lead outline packages:
CD40160 CD40161 CD40162 CD40163
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H1F
H6P
H4X
H1F
H6W
H4X
H1L
H6P
H4W
H1F
H6W
Features
• High-Voltage Types (20V Rating)
• CD40160BMS Decade with Asynchronous Clear
• CD40161BMS Binary with Asynchronous Clear
• CD40162BMS Decade with Synchronous Clear
• CD40163BMS Binary with Synchronous Clear
• Internal Look-Ahead for Fast Counting
• Carry Output for Cascading
• Synchronously Programmable
• Clear Asynchronous Input (CD40160BMS, CD40161BMS)
• Clear Synchronous Input (CD40162BMS, CD40163BMS)
• Synchronous Load Control Input
• Low Power TTL Compatibility
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package
Temperature Range; 100nA at 18V and +25
o
C
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series CMOS
Devices”
Applications
• Programmable Binary and Decade Counting
• Counter Control/Timers
• Frequency Dividing
Pinout
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TOP VIEW
Functional Diagram
PE
CLEAR 1
CLOCK 2
P1 3
P2 4
P3 5
P4 6
PE 7
VSS 8
16 VDD
15 CARRY OUT
14 Q1
13 Q2
12 Q3
11 Q4
10 TE
9 LOAD
VDD = 16
VSS = 8
TE
CLEAR
LOAD
CLOCK
P1
P2
P3
P4
7
10
1
9
2
3
4
5
6
15
CARRY
OUT
11
Q4
12
Q3
13
Q2
14
Q1
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input.
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
±
1/32 Inch (1.59mm
±
0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance. . . . . . . . . . . . . . . .
θ
ja
θ
jc
o
C/W
o
C/W
Ceramic DIP and FRIT Package . . . .
80
20
Flatpack Package . . . . . . . . . . . . . . . .
70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For T
A
= -55
o
C to +100
o
C (Package Type D, F, K). . . . . . .500mW
For T
A
= +100
o
C to +125
o
C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW
For T
A
= Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1
2
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
3
1
2
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
3
1
2
VDD = 18V
Output Voltage
Output Voltage
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
VOL15
VOH15
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VNTH
VPTH
F
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
VIL
VIH
VIL
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
3
1, 2, 3
1, 2, 3
1
1
1
1
1
1
1
1
1
7
7
8A
8B
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
LIMITS
TEMPERATURE
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
-
3.5
-
11
1.5
-
4
-
V
V
V
V
MIN
-
-
-
-100
-1000
-100
-
-
-
-
14.95
0.53
1.4
3.5
-
-
-
-
-2.8
0.7
MAX
10
1000
10
-
-
-
100
1000
100
50
-
-
-
-
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
UNITS
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
mA
mA
mA
mA
mA
mA
mA
V
V
V
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
(NOTE 1)
VDD = 20V, VIN = VDD or GND
VOH > VOL <
VDD/2 VDD/2
NOTES: 1. All voltages referenced to device GND, 100% testing being im-
plemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is
0.050V max.
4-2
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
TTHL
TTLH
FCL
VDD = 5V, VIN = VDD or GND
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
LIMITS
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
MIN
-
-
-
-
-
-
-
-
-
-
2
1.48
MAX
400
540
450
608
250
338
500
675
200
270
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
PARAMETER
Propagation Delay
Clock to Q
Propagation Delay
Clock to COut
Propagation Delay
TE to COut
Propagation Delay
CD40160BMS,
CD40161BMS Clear to Q
Transition Time
SYMBOL
TPHL1
TPLH1
TPHL2
TPLH2
TPHL3
TPLH3
TPHL4
CONDITIONS
(NOTE 1, 2)
VDD = 5V, VIN = VDD or GND
Maximum Clock Input Fre-
quency
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
NOTES
1, 2
TEMPERATURE
-55
o
C, +25
o
C
+125
o
C
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
+25
o
C, +125
o
C, -
55
o
C
+25
o
C, +125
o
C, -
55
o
C
+25
o
C, +125
o
C, -
55
o
C
+25
o
C, +125
o
C, -
55
o
C
+125
o
C
-55
o
C
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
+125
o
C
-55
o
C
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
+125
o
C
-55
o
C
MIN
-
-
-
-
-
-
-
-
4.95
9.95
0.36
0.64
0.9
1.6
2.4
4.2
-
-
-
-
-
-
MAX
5
150
10
300
10
600
50
50
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
UNITS
µA
µA
µA
µA
µA
µA
mV
mV
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
4-3
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Output Current (Source)
SYMBOL
IOH15
CONDITIONS
VDD =15V, VOUT = 13.5V
NOTES
1, 2
TEMPERATURE
+125
o
C
-55
o
C
Input Voltage Low
Input Voltage High
Propagation Delay
Clock to Q
Propagation Delay
Clock to C Out
Propagation Delay
TE to C Out
Propagation Delay
CD40160BMS,
CD40161BMS Clear to Q
Transition Time
VIL
VIH
TPHL1
TPLH1
TPHL2
TPLH2
TPHL3
TPLH3
TPHL4
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
TTHL
TTLH
FCL
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
TRCL
TFCL
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Data Hold Time
Clock Operation
TH
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Clock Pulse
Width
Clock Operation
Minimum Setup Time
Data to Clock
TW
VDD = 5V
VDD = 10V
VDD = 15V
TS
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Setup Time
Load to Clock
TS
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Setup Time PE
to TE to Clock
TS
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Clear Pulse
Width (CD40160BMS,
CD40161BMS)
Minimum Setup Time
Clear to Clock
(CD40162BMS,
CD40163BMS)
Minimum Hold Time
Clear to Clock
(CD40162BMS,
CD40163BMS)
TW
VDD = 5V
VDD = 10V
VDD = 15V
TS
VDD = 5V
VDD = 10V
VDD = 15V
TH
VDD = 5V
VDD = 10V
VDD = 15V
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
+25
o
C, +125
o
C, -
55
o
C
+25
o
C, +125
o
C, -
55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-
-
7
-
-
-
-
-
-
-
-
-
-
5.5
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
-2.4
-4.2
3
-
160
120
190
140
110
80
220
160
100
80
-
-
200
70
15
0
0
0
170
70
50
240
90
60
240
90
60
340
140
100
170
70
50
340
140
100
0
0
0
UNITS
mA
mA
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Maximum Clock Input Fre-
quency
Maximum Clock Rise or
Fall Time
4-4
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Minimum Clear Removal
Time
(CD40160BMS,
CD40161BMS)
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of
the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage Delta
P Threshold Voltage
P Threshold Voltage Delta
Functional
SYMBOL
IDD
VNTH
∆VTN
VTP
∆VTP
F
CONDITIONS
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
1, 2, 3, 4
+25
o
C
NOTES
1, 4
1, 4
1, 4
1, 4
1, 4
1
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-2.8
-
0.2
-
VOH >
VDD/2
-
MAX
25
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25
o
C
Limit
UNITS
µA
V
V
V
V
V
SYMBOL
TREM
CONDITIONS
VDD = 5V
VDD = 10V
VDD = 15V
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
MIN
-
-
-
MAX
200
100
70
UNITS
ns
ns
ns
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25
o
C limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
o
C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
IOL5
IOH5A
±
1.0µA
±
20% x Pre-Test Reading
±
20% x Pre-Test Reading
DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B
Group D
Subgroup B-5
Subgroup B-6
MIL-STD-883
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2 3
Subgroups 1, 2, 3, 9, 10, 11
IDD, IOL5, IOH5A
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
4-5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
