CY28359
273 MHz 6 Output Buffer for DDR400 DIMMS
Features
• Dual 1- to 3-output buffer/driver
• Supports up to 2 DDR DIMMs
• Outputs are individually enabled/disabled
• Low-skew outputs (< 100 ps)
• Supports 266 MHz, 333 MHz and 400 MHz DDR SDRAM
• SMBus Read and Write support
• Space-saving 28-pin SSOP package
Functional Description
The CY28359 is a 2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 6 differ-
ential outputs. Designers can configure these outputs to
support up to two DDR DIMMs. The CY28359 can be used in
conjunction with the CY28326 or similar clock synthesizer for
the VIA P4X600 chipset.
The CY28359 also includes an SMBus interface which can
enable or disable each output clock. On power-up, all output
clocks are enabled.
Block Diagram
BUF_INA
FB_OUTA
DDRAT0
DDRAC0
DDRAT1
DDRAC1
DDRAT2
DDRAC2
DDRBT0
DDRBC0
DDRBT1
DDRBC1
DDRBT2
DDRBC2
FB_OUTB
Pin Configuration
FB_OUTB
BUF_INB
DDRBT0
DDRBC0
DDRBT1
DDRBC1
VDD
VSS
FB_OUTA
BUF_INA
VSS
DDRAT0
DDRAC0
DDRAT1
SDATA
SEL_ADDR
SCLK
SMBus
Decoding
BUFF_INB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VSS
SEL_ADDR
DDRBT2
DDRBC2
VSS
VDD
DDRAT2
DDRAC2
SDATA
SCLK
VSS
VDD
DDRAC1
28 PIN SSOP
CY28359
Rev 1.0, November 24, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 7
www.SpectraLinear.com
CY28359
Pin Description
Pin
10
2
13,15,20
4,6,24
12,14,21
3,5,25
9
1
18
19
26
7,16,22,28
8,11,17,23,27
Name
BUF_INA,
BUF_INB
DDRA[0:2]C
DDRB[0:2]C
DDRA[0:2]T
DDRB[0:2]T
FB_OUTA
FB_OUTB
SCLK
SDATA
SEL_ADDR
VDD2.5
VSS
PWR
VDD2.5
VDD2.5
VDD2.5
VDD2.5
VDD2.5
VDD2.5
I/O
I
O
O
O
I
I/O
I
Description
Reference input from chipset.
2.5V input.
Clock outputs.
These outputs provide complementary
copies of BUF_INA & BUF_INB, respectively.
Clock outputs.
These outputs provide copies of BUF_INA
& BUF_INB, respectively.
Feedback clock for chipset
SMBus clock input. Has pull-up resistor
SMBus data input. Has pull-up resistor
Address Select Pin. Has pull-down resistor
2.5V voltage supply
Ground
controller. For Block Write/Read operation, the bytes must be
accessed in sequential order from lowest to highest byte (most
significant bit first) with the ability to stop after any complete
byte has been transferred. For Byte Write and Byte Read
operations, the system controller can access individual
indexed bytes. The offset of the indexed byte is encoded in the
command code, as described in
Table 1.
The Block Write and Block Read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding Byte Write and Byte
Read protocol.The slave receiver address is 11010010 (D2h)
or 11011100 (DCh) depending on state of ADDRSEL.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. The interface can also be
accessed during power down operation.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write and Block Read operation from any external I
2
C
Table 1. Command Code Definition
Bit
7
(6:5)
(4:0)
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
01
Description
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be '00000'
Rev 1.0, November 24, 2006
Page 2 of 7
CY28359
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
....
....
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
Data Byte (N–1) – 8 bits
Acknowledge from slave
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte N from slave – 8 bits
Acknowledge from master
Stop
Block Read Protocol
Description
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'1XXxxxxx' stands for byte operation,bit[6:5] for
Device selection bits for multiple device selection,
bits[4:0] of the command code represents the offset
of the byte to be accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'1XXxxxxx' stands for byte operation,bit[6:5] for
Device selection bits for multiple device selection,
bits[4:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Acknowledge from master
Stop
Byte Read Protocol
Description
19
20:27
28
29
19
20
21:27
28
29
30:37
38
40
Rev 1.0, November 24, 2006
Page 3 of 7
CY28359
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
SMBus Address for the CY28359 when SEL_ADDR=1:
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
SMBus Address for the CY28359 when SEL_ADDR=0:
A6
1
A5
1
A4
0
A3
1
A2
1
A1
1
A0
0
R/W
----
Byte 22: Outputs Active/Inactive Register (1 = Active, 0 = Three-state), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
--
24, 25
--
--
--
9
1
Pin #
Description
Input Threshold Control00: Normal (1.25V)
01: 1.20V
10: 1.15V
11: 1.35V
FBOUTA
0 = Enable, 1 = Disable
FBOUTB
0 = Enable, 1 = Disable
Reserved, drive to 0
Reserved, drive to 0
DDRBT2, DDRBC2
Reserved, drive to 0
Default
0
0
0
0
1
1
1
1
Byte 23: Outputs Active/Inactive Register(1 = Active, 0 = Three-state), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
5,6
3,4
21,20
--
14,15
12,13
--
--
Pin #
DDRBT1, DDRBC1
DDRBT0, DDRBC0
DDRAT2, DDRAC2
Reserved, drive to 0
DDRAT1, DDRAC1
DDRAT0, DDRAC0
Reserved, drive to 0
Reserved, drive to 0
Description
Default
1
1
1
1
1
1
1
1
Rev 1.0, November 24, 2006
Page 4 of 7
CY28359
Absolute Maximum Conditions
Supply Voltage to Ground Potential..................–0.5 to +4.0V
DC Input Voltage (except BUF_IN)............ –0.5V to V
DD
+0.5
Storage Temperature .................................. –65°C to +150°C
Static Discharge Voltage ........................................... >2000V
(per MIL-STD-883, Method 3015)
Operating Conditions
Parameter
V
DD2.5
T
A
C
OUT
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Output Capacitance
Input Capacitance
Description
Min.
2.375
–40
–
–
Typ.
–
–
6
5
Max.
2.625
85
–
–
Unit
V
°C
pF
pF
Electrical Characteristics
Over the Operating Range
Parameter
V
IL
V
IH
I
IL
I
IH
I
OH
I
OL
V
OL
V
OH
I
DD
I
DD
V
OUT
V
OC
IN
DC
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output HIGH Current
Output LOW Current
Output LOW Voltage
Output HIGH Voltage
Supply Current
Supply Current
Output Voltage Swing
Output Crossing Voltage
Input Clock Duty Cycle
.
V
IN
= 0V
V
IN
= V
DD
V
DD
= 2.375V
V
OUT
= 1V
V
DD
= 2.375V
V
OUT
= 1.2V
I
OL
= 12 mA, V
DD
= 2.375V
I
OH
= –12 mA, V
DD
= 2.375V
Unloaded outputs, 273 MHz
Loaded outputs, 273 MHz
See Test Circuitry (Refer to
Figure 1)
Test Conditions
For all pins except SMBus
Min.
–
2.0
–
–
–18
26
–
1.7
–
–
0.7
(V
DD
/2) – 0.2
48
Typ.
–
–
–
–
–32
35
–
–
–
–
–
V
DD
/2
Max.
0.8
–
5
5
–
–
0.6
–
250
300
V
DD
+ 0.6
(V
DD
/2) + 0.2
52
Unit
V
V
A
A
mA
mA
V
V
mA
mA
V
V
%
Switching
Parameter
F
O
T
DC
t
3
t
4
Characteristics
[1]
Name
Operating Frequency
Duty Cycle = t
2
t
1
DDR Rising/Falling Edge Rate
[2]
Output to Output Skew
[2]
Measured between 20% to 80% of
output (Refer to
Figure 1)
All outputs equally loaded
Test Conditions
Min.
66
Measured at V
DD/
2 for 2.5V outputs. IN
DC
– 2%
1
–
Typ.
–
–
–
–
Max.
273
IN
DC
+ 2%
3
100
Unit
MHz
%
V/ns
ps
Notes:
1. Parameter is guaranteed by design and characterization. Not 100% tested in production
2. All parameters specified with loaded outputs.
Rev 1.0, November 24, 2006
Page 5 of 7
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