A42L2604 Series
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Features
Organization: 4,194,304 words X 4 bits
Part Identification
- A42L2604 (2K Ref.)
Single 3.3V power supply/built-in VBB generator
Low power consumption
- Operating: 80mA (-45 max)
-
Standby: 1.0mA (TTL), 1.5mA (CMOS),
350µA (Self-refresh current)
High speed
- 45/50 ns
RAS access time
- 20/22 ns column address access time
-
12/13 ns CAS access time
-
18/20 ns EDO Page Mode Cycle Time
Industrial operating temperature range: -40
°
C to +85
°
C
for -U
Fast Page Mode with Extended Data Out
2K Refresh Cycle in 32ms
Read-modify-write, RAS -only, CAS -before- RAS ,
Hidden refresh capability
TTL-compatible, three-state I/O
JEDEC standard packages
-
300mil, 24/26-pin SOJ
-
300mil, 24/26-pin TSOP type II package
General Description
The A42L2604 is a new generation randomly accessed
memory for graphics, organized in a 4,194,304-word by 4-
bit configuration. This product can execute Write and
Read operation via
CAS
pin.
The A42L2604 offers an accelerated Fast Page Mode
cycle with a feature called Extended Data Out (EDO).
This allow random access of up to 2048(2K Ref.) words
within a row at a 56/50 MHz EDO cycle, making the
A42L2604 ideally suited for graphics, digital signal
processing and high performance computing systems.
Pin Configuration
SOJ
TSOP
Pin Descriptions
Symbol
Description
A0 – A10
VCC
I/O
0
I/O
1
WE
RAS
NC
1
2
3
4
26
25
24
23
VSS
I/O
3
I/O
2
CAS
OE
A9
VCC
I/O
0
I/O
1
WE
RAS
NC
1
2
3
4
26
25
24
23
VSS
I/O
3
I/O
2
CAS
OE
A9
Address Inputs (2K product)
Data Input/Output
Row Address Strobe
Column Address Strobe
Write Enable
Output Enable
3.3V Power Supply
Ground
No Connection
I/O
0
- I/O
3
RAS
5
6
22
21
5
6
22
21
CAS
WE
OE
VCC
VSS
NC
A42L2604S
A42L2604V
A10
A0
A1
A2
A3
VCC
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
A10
A0
A1
A2
A3
VCC
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
(April, 2004, Version 1.1)
1
AMIC Technology, Corp.
A42L2604 Series
Selection Guide
Symbol
Description
-45
-50
Unit
t
RAC
t
AA
t
CAC
t
OEA
t
RC
t
PC
Maximum RAS Access Time
Maximum Column Address Access Time
Maximum CAS Access Time
Maximum Output Enable ( OE ) Access Time
Minimum Read or Write Cycle Time
Minimum EDO Cycle Time
45
20
12
12
76
18
50
22
13
13
84
20
ns
ns
ns
ns
ns
ns
Functional Description
The A42L2604 reads and writes data by multiplexing an 22-
bit address into a 11-bit(2K) row and column address.
RAS
and
CAS
are used to strobe the row address and the
column address, respectively.
A Read cycle is performed by holding the WE signal high
during RAS /
CAS
operation. A Write cycle is executed by
holding the WE signal low during RAS /
CAS
operation;
the input data is latched by the falling edge of WE or
CAS
, whichever occurs later. The data inputs and outputs
are routed through 4 common I/O pins, with RAS ,
CAS
,
WE and OE controlling the in direction.
EDO Page Mode operation all 2048(2K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS
. While holding RAS low,
CAS
can be toggled to
strobe changing column addresses, thus achieving shorter
cycle times.
The A42L2604 offers an accelerated Fast Page Mode cycle
through a feature called Extended Data Out, which keeps
the output drivers on during the
CAS
precharge time (t
cp
).
Since data can be output after
CAS
goes high, the user is
not required to wait for valid data to appear before starting
the next access cycle. Data-out will remain valid as long as
RAS and OE are low, and WE is high; this is the only
characteristic which differentiates Extended Data Out
operation from a standard Read or Fast Page Read.
A memory cycle is terminated by returning both RAS and
CAS
high. Memory cell data will retain its correct state by
maintaining power and accessing all 2048(2K)
combinations of the 11-bit(2K) row addresses, regardless of
sequence, at least once every 32ms through any RAS
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and
CAS
.
It is recommended that RAS and
CAS
track with VCC or
be held at a valid V
IH
during Power-On to avoid current
surges.
(April, 2004, Version 1.1)
2
AMIC Technology, Corp.
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