CY28443-3
Clock Generator for Intel Calistoga Chipset
Features
• Compliant to Intel
®
CK410M
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 27 MHz Spread and Non-spread video clock
• 48 MHz USB clocks
• SRC clocks independently stoppable through
CLKREQ#[A:B]
• 96 /100-MHz Spreadable differential video clock.
CPU
SRC
PCI REF DOT96 USB_48M LCD 27M
x6
x1
x1
x1
x1
x2
x2 / x3 x5/6/7
• 33 MHz PCI clock
• Buffered Reference Clock 14.318 MHz
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-Pin SSOP/TSSOP packages
Block Diagram
XIN
XOUT
SEL_CLKREQ
PCI_STP#
CPU_STP#
CLKREQ[A:B]#
ITP_SEL
FS[C:A]
14.318M
Hz
Crystal
PLL Reference
VDD
REF1
IREF
VDD
CPUT[0:1]
CPUC[0:1]
VDD
CPUT2_ITP/SRCT11
CPUC2_ITP/SRCC11
VDD
SRCT([2:5],[8:9])
SRCC([2:5],[8:9])
VDD
PCI[3:5]
VDD_PCI
PCIF[0:1]
VDD
SRCT0/100M
T_SST
SRCC0/100M
C_SST
VDD48
27MSpread
VDD48
DOT96T
DOT96C
VDD48
48M
27M
PLL
VTT_PWRGD#/PD
SDATA
SCLK
I2C
Logic
Pin Configuration
VDD
VSS
PCI3
PCI4
PCI5 / FCT_SEL1
VSS
VDD
ITP_SEL / PCIF0
PCIF1
VTT#/PD
VDD
FSA / 48M
VSS
DOT96T / 27M non-spread
DOT96C / 27M_25M spread
FSB
SRCT0 / 100MT_SST
SRCC0 / 100MC_SST
SRCT2
SRCC2
VDD
SRCT3
SRCC3
SRCT4
SRCC4
SRCT5 _SATA
SRCC5_SATA
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI2 / SEL_CLKREQ
PCI_STP#
CPU_STP#
FSC
REF1/FCTSEL0
VSS
XIN
XOUT
VDD
SDATA
SCLK
VSS
CPUT0
CPUC0
VDD
CPUT1
CPUC1
IREF
VSS
VDD
CPUT2_ITP/SRCT11
CPUC2_ITP/SRCC11
VDD
SRCT9 / CLKREQ9
SRCC9 /CLKREQ8
SRCT8
SRCC8
VSS
CPU
PLL
Divider
LVDS
PLL
FCTSEL1
Divider
Fixed
PLL
Divider
Divider
VDD48
27MNon-spread
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
CY28443-3
Page 1 of 23
www.SpectraLinear.com
CY28443-3
Pin Descriptions
Pin No.
1, 7, 11, 21, VDD
28, 34, 42, 48
2, 6, 13, 29,
45, 51
3,4
5
VSS
PCI[3:4]
PCI5/FCTSEL1
Name
Type
PWR
GND
3.3V power supply.
Ground.
Description
O, SE
33-MHz clock.
O, SE
33-MHz clock/3.3 LVTTL input for selecting for pin 14, 15 (DOT96[T/C],
PD
27M-non-spread and Spread) and pin 17,18 (SRC[T/C]0 or 100M[T/C]_SST)
(sampled on the VTT_PWRGD# assertion).
FCTSEL1 FCTSEL0 PIN 14
PIN 15
0
0
DOT96T
DOT96C
0
1
DOT96T
DOT96C
1
0
27M_non spread 27M_Spread
1
1
OFF Low
TBD
PIN 17
100MT_SST
SRCT0
SRCT0
SRCT0
PIN 18
100MC_SST
SRCC0
SRCC0
SRCC0
8
ITP_SEL/PCIF0
I/O, SE
3.3V LVTTL input to enable SRC[T/C]11or CPU[T/C]2_ITP/33-MHz clock
output.
(sampled on the VTT_PWRGD# assertion).
1 = CPU_ITP, 0 = SRC11
I/O, SE
33-MHz clock.
I, PU
3.3V LVTTL input.
This pin is a level sensitive strobe used to latch the FS[C:A],
ITP_SEL, FCTSEL[1:0], SEL_CLKREQ#. After VTT_PWRGD# (active LOW)
assertion, this pin becomes a real-time input for asserting power-down (active
HIGH).
3.3V-tolerant input for CPU frequency selection/Fixed 48-MHz clock output.
Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications.
9
10
PCIF1
VTT_PWRGD#/PD
12
14, 15
FSA/48M
I/O
O, DIF
Fixed 96-MHz Differential Clock/ Single ended 27-MHz clocks.
When
DOT96T/27M_non
configured for 27-MHz, only the clock on pin 15 contains spread. Selected via
spread
FCTSEL[0:1] at VTT_PWRGD# assertion.
DOT96C/27M_Spread
FSB
SRC[T/C]0/
100M[T/C]_SST
I
3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications
16
17,18
O,DIF
100-MHz Differential Serial Reference Clock/ 100-MHz LVDS Differential
Clock.
O, DIF
100-MHz Differential Serial Reference Clocks.
O, DIF
Differential serial reference clock.
Recommended output for SATA.
I/O, PU
3.3V LVTTL input for enabling assigned SRC clock (active LOW) / 100-MHz
Serial Reference Clock.
Default function is CLKREQ#
19,20,22,23, SRC[T/C]
24,25,30,31
26,27
33,32
SRC[T/C]5_SATA
SRCT9/CLKREQ#A,
SRCC9/CLKREQ#B
36,35
CPUT2_ITP/SRCT11, O, DIF
Selectable differential CPU / SRC clock output.
CPUC2_ITP/SRCC11
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC11,
ITP_EN = 1@ VTT_PWRGD# assertion =CPU2_ITP
VDDA
VSSA
IREF
CPU[T/C][0:1]
SCLK
SDATA
XOUT
XIN
PWR
GND
I
3.3V power supply for PLL.
Ground for PLL.
A precision resistor is attached to this pin,
which is connected to the internal
current reference.
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
37
38
39
44,43,41,40
46
47
49
50
O, DIF
Differential CPU clock outputs.
I
I/O
OD
I
O, SE
14.318-MHz crystal output.
14.318-MHz crystal input.
Rev 1.0, November 20, 2006
Page 2 of 23
CY28443-3
Pin Descriptions
(continued)
Pin No.
52
Name
REF1/FCTSEL0
Type
Description
I/O, SE
Fixed 14.318-MHz Clock Output/3.3 LVTTL input for selecting for pin 14, 15
PD
(DOT96[T/C], 27M-non-spread and Spread) and pin 17,18 (SRC[T/C]0 or
100M[T/C]_SST)
(sampled on the VTT_PWRGD# assertion).
FCTSEL1 FCTSEL0 PIN 14
PIN 15
0
0
DOT96T
DOT96C
0
1
DOT96T
DOT96C
1
0
27M_non spread 27M_Spread
1
1
OFF Low
TBD
PIN 17
100MT_SST
SRCT0
SRCT0
SRCT0
PIN 18
100MC_SST
SRCC0
SRCC0
SRCC0
53
FSC
I/O
3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specification Table for VilFS_C, VimFS_C and VihFS_C
specifications
3.3V LVTTL input for CPU_STP# active LOW.
3.3V LVTTL input for PCI_STP# active LOW.
54
55
56
CPU_STP#
PCI_STP#
I, PU
I, PU
PCI2/SEL_CLKREQ# I/O, PD
Fixed 33-MHz clock output/3.3V-tolerant input for CLKREQ# pins 32 and 33
SE
selection
(sampled on the VTT_PWRGD# assertion).
0 = CLKREQ#[A:B] functionality
1 = SRC[T/C]9 functionality
Table 1. Frequency Select Table FSA, FSB and FSC
FSC
1
0
0
0
FSB
0
0
1
1
FSA
1
1
1
0
CPU
100 MHz
133 MHz
166 MHz
200 MHz
SRC
100 MHz
100 MHz
100 MHz
100 MHz
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
27MHz
27 MHz
27 MHz
27 MHz
27 MHz
REF0
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
USB
48 MHz
48 MHz
48 MHz
48 MHz
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode.
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 2.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Rev 1.0, November 20, 2006
Page 3 of 23
CY28443-3
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
Rev 1.0, November 20, 2006
Page 4 of 23
CY28443-3
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
RESERVED
RESERVED
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
RESERVED
SRC[T/C]0
/100M[T/C]_SST
Description
RESERVED
RESERVED
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
RESERVED, Set = 1
SRC[T/C]0 /100M[T/C]_SST Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
0
Name
PCIF0
27M_nss_DOT_96[T/C]
USB_48MHz
RESERVED
REF1
CPU[T/C]1
CPU[T/C]0
CPU, SRC, PCI, PCIF
spread enable
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
27M nonspread and DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB_48M MHz Output Enable
0 = Disabled, 1 = Enabled
RESERVED
REF1 Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Description
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
PCI5
PCI4
PCI3
PCI2
RESERVED
RESERVED
CPU[T/C]2
PCIF1
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
RESERVED
RESERVED
CPU[T/C]2 Output Enable
0 = Disabled (Hi-Z), 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Description
Rev 1.0, November 20, 2006
Page 5 of 23
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