Inrush Limiter/Circuit Breaker/Hotswap Controller IC
(No External Parts Required)
Features
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No External Parts Required
On Board 80V, 2A MOSFET
No Rsense Needed
±8.0V
to
±80V
Input Voltage Range
Two Level Current Limiting
❍
1.2A Initial Inrush Limit
❍
2.0A Second Inrush Limit/Circuit Breaker Triggers
Servo Limit to 1.2A for T
oc
then shuts down
Fast Response Current Limit when Over Current or Step
Voltage at Input Supply (eg. Diode ‘OR’ing)
UVLO/ENABLE & POR Supervisory Circuits
Programmable UVLO
Over Current Protection
9.0sec Auto Retry
Built in Thermal Shutdown with Hysteresis
80V Open Drain PWRGD bar Flag
Thermally Rugged DPAK5 Package
Description
The HV111 is a complete power management solution for
switched or pluggable backplane applications up to 1.65A,
running from –8.0 to -80V, requiring no external components
or programming in many applications.
The HV111 is not
limited to only negative input voltages. It can also be
used in +8.0 to +80V systems.
An internally programmed supervisor UVLO/ ENABLE may
be overridden with external resistors for custom settings.
Satisfying this supervisor will begin a POR phase to ensure
de-bouncing. Thereafter, a servo loop controls an internal
80V, 2A pass element to limit current. The circuit uses
internal mirrors to measure current, eliminating the need for
a sense resistor.
The HV111 includes two current modes: i) initial current limit
mode limits the current to 1.2A during turn on; ii) thereafter a
2A monitor circuit will re-trigger the servo mechanism back
to 1.2A limit if it is tripped. An on-board thermal supervisor
ensures that the device can never be damaged by over
current conditions.
Circuit breaker functionality is obtained through a either a
current limit timeout or a PWM current limiter for severe
faults. If the servo limits for more than 75ms then the part
will shut down the pass element, and initiate a 9sec timer
after which the turn on sequence will restart.
The HV111 is available in a thermally rugged DPAK-5
package which provides improved thermal resistance when
compared to SO-8 based solutions.
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Applications
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Power Ethernet Systems
Routers, Switches
Chargers
Security Peripherals & Cameras
Automotive Protection
Negative Supply Rail Breaking Applications
Networking Line Cards
Telecom Line Cards
Typical Schematics and Waveforms
INRUSH
PWRGD
*
DRAIN
*
GND*
*Referred to –48V
7/24/03
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate
"products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined
to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest
product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the
Legal/Disclaimer page on the Supertex website.
HV111
Ordering Information
Package Options
DEVICE
DPAK-5
HV111
HV111K4
Absolute Maximum Ratings
Supply Voltage*, V
pp
Operating Temperature Range
Storage Temperature Range
5 Pin DPAK Thermal Resistance R
θ
JA
5 Pin DPAK Thermal Resistance R
θ
JC
* Relative to V
NN
-0.5V to 90V
-40°C to +85°C
-65° to +150°C
80°C/W
11°C/W
Electrical Characteristics
( * means -20°C< T < +85°C)
A
Symbol
Parameter
Min
Typ
Max
Units
T
A
Conditions
V
PP
I
PP
V
UVLO
V
HYS
V
UV
V
UVHYS
R
UVLO
R
DS
I
LEAK
I
INRUSH
I
CB
I
LIMIT
I
SC
VOL
PWRGD
IOH
PWRGD
t
SC
t
OC
t
LIMIT
t
POR
t
RESTART
T
OVER
T
RESET
Supply Voltage
Supply Current
Internal UVLO Threshold (High to
Low ie. Turning Off)
Internal UVLO Hysteresis
UVLO Comparator Threshold
UVLO Comparator Hysteresis
UVLO Input Resistance
MOSFET On Resistance
Output Leakage Current
Inrush Current Limit
Circuit Breaker Trip Current
Over Load Current Limiting
Shorted Circuit PWM Average
Current
PWRGD Output Low Voltage
PWRGD Output leakage Current
Shorted-Circuit Timer
Over-Current Timer
Current Limit Delay Time
POR Timer
Restart Timer (4)
Over Temperature Trip Point
Temperature Reset
(1) (4)
(2) (4)
(3)
-80
-23.5
1.5
1.10
60
78
-26.0
2.5
1.20
100
111
1
1.15
1.65
1.40
2.00
1.2
230
-8.0
1
-28.5
3.5
1.30
140
144
1.5
10
1.65
2.35
V
mA
V
V
V
mV
kΩ
Ω
µA
A
*
*
*
*
*
*
*
*
*
V
PP
– V
NN
V
NN
= -48V, Standby Mode
Subtract V
HYS
for Low-to-High
Referenced to V
NN
MOSFET is off
Trips then limits to I
LIMIT
until toc
expires.
V
PP
-V
DRAIN
< ~1V
I=1mA; Reference to V
NN
A
mA
0.4
10
V
µA
ms
ms
µs
6.5
150
100
ms
Sec
°C
°C
*
*
*
*
*
*
*
*
*
V=5V; Reference to V
NN
40
40
75
75
10
110
110
Limits within 10µs. May take
up to 100µs to reach final level.
2.5
120
70
4.5
9
135
Low to High
High to Low
(1) Shorted-circuit timer starts after POR timer. If V
DS
drops more than ¼(V
PP
-V
NN
) after t
SC
then a shorted-circuit condition exists.
(2) If the output current is in an overload condition then the output immediately goes to current limit and starts the over-current timer. If I
OUT
does not drop back
below I
LIMIT
before the timer expires then an over current condition exists. The timer is immediately reset when a fault is cleared.
(3) Time for fast return to limit circuit to react.
(4) Guaranteed by design.
2
HV111
Pin Description
V
PP
HV111
Regulator
M2
PWRGD
V
PP
–
Positive voltage supply input
V
NN
– Negative voltage power supply input
DRAIN
– Internal N-Channel MOSFET drain output
UVLO/ENABLE
– Under Voltage lockout input or Enable
PWRGD
– Active Low Power Good Output
UVLO/
Enable
UVLO
DRAIN
CONTROL
POR Timer
LOGIC
D
Temperature
Sense
V
NN
M1
Restart
TImer
1
2000
M0
S
V
NN
EN UV PP
AB LO
LE /
PW
V
Figure 1
−
Internal Blocks of HV111
Many systems include front end capacitance to provide low
impedance energy and filtering to power systems. These
systems include hot pluggable live-backplane systems, such
as –48V telecom systems and switched systems such as
battery connected backed-up loads.
This filter capacitance, usually implemented as large
electrolytic capacitors, looks like a low impedance
connected directly across the power supply terminals and
causes high inrush currents which could damage
connectors, traces or components (such as the capacitors
themselves). These high currents may also cause localized
glitching of the backplane or EMI that could reset or interrupt
surrounding circuit cards.
The HV111 is a single chip solution that provides bullet-
proof power management control for systems with loads
less than 1.65A. See Thermal Shutdown section for power
dissipation limitation. The HV111 does not require the use of
any external components or programming and eliminates
the need for a sense resistor. Where desired, however,
internal set points may be overridden with external
components – for example an external resistor divider may
be used to set the UVLO/ENABLE threshold.
Turn on Protection
(UVLO/POR for Debounce + PWM limit)
PWM I
limit
DR
Functional Description
RG
D
AI
N
I
DS
200mA/div
V
PP
-V
NN
POR
High Voltage Regulator
The HV111 includes a high voltage regulator capable of
operation with V
PP
-V
NN
=8.0V to 80V. The regulator provides
an internal voltage to operate circuitry and drive the internal
1Ω MOSFET pass element.
Figure 2
−
UVLO & POR + Dead Short Protection
The second subsystem is the UVLO/POR that work together
to debounce. Leave the UVLO input open to use the default
setting of –26V with 2.5V hysteresis. This default setting can
be over driven with an external resistive divider. The
comparator threshold is 1.2V with respect to V
NN
. The HV111
is capable of operation down to 8.0V for automotive
applications to 80V for the most rugged telecom
applications.
The third subsystem, PWM Iimit, is protection for turning on
into a short (or a later dead short). In this case the HV111
helps avoid the dumping of large currents into the load by
pulse width modulating (PWM) the current to limit Inrush
current to <250mA average if V
pp
-V
DRAIN
<~1V.
3
HV111
Programming UVLO
GND
V
PP
V
PP
V
PP
R1
2.4MΩ
1mA
R
1
Enable
PWRGD
UVLO
Q
1
R2
116k
1.2V
V
NN
V
NN
-48V
Internal to
HV111
DRAIN
Figure 3
−
Programming UVLO
The UVLO/ENABLE pin makes it easy to override the
internal 26V nominal under voltage. The 26V nominal setting
is produced by a resistor divider of 2.4MΩ and 116k. These
are 20% resistors, however, 1% accurate relative to one
another. To override there are two options. The first is to
simply use a much lower impedance divider, for example
200k, and largely ignore the internal divider. Alternatively,
the internal impedance may be taken into a account in the
network and the UVLO calculated as:
V
PP
*(R2||116k) / (R1||2.4MΩ+R2||116k)
Keep in mind, however, that the 30% variation on the
internal resistors will reduce the accuracy of the UVLO set
point using this approach.
Note that the UVLO/ENABLE pin may also be used as an
enable with a nominal 1.20V trip point and 10% of
hysteresis.
Figure 4
−
PWRGD Active High
The above circuit works as follows for ACTIVE HIGH
operation. If the PWRGD is low, then the current sourced by
the pullup is pulled to V
NN
and the BJT, Q1, is starved for
base drive current and remains off. The reverse Vbe voltage
is protected by the series diode, D1. If PWRGD is open,
then the current has no alternative but to flow into the base
and thus connects the DC/DC ENABLE pin to the DC/DC
ground reference (DRAIN pin of the HV111). As the clamp is
inverting, therefore proper ACTIVE high polarity is
established.
The resistor, R1, should be sized as V
PP
/1mA to ensure that
the maximum PWRGD transistor current is not exceeded
(remember to use the maximum possible V
PP
your circuit will
see rather than the nominal value of V
PP
).
Further, Q1 must be rated for operation to maximum
expected V
PP
and have a beta large enough that the
minimum V
PP
min/V
PP
max*1mA*β
min
> Ipullupmax of the
DC/DC converter (or external resistor if used).
optional
GND
PWRGD Active High or Active Low
(for DC/DC HV Interface / Enable)
The PWRGD pin is an open drain active low MOSFET which
is enabled when the gate voltage on the internal power
MOSFET reaches its full on voltage. The PWRGD output is
nominally ACTIVE LOW, however, the simple circuit shown
(Figure 4) can convert it to active high operation.
-48V
BAT
DC/DC
V
PP
DC/DC
V
O
PWRGD
UVLO/
Enable
ENABLE
GND
V
NN
DRAIN
HV111
Figure 5
−
PWRGD Enable
Also shown in Figure 5 is decoupling capacitor is not strictly
required, a fast dv/dt on PWRGD bar can result in coupling
that can glitch the UVLO pin. This decoupling capacitor
ensures that glitches will be eliminated.
4
HV111
Thermal Shutdown
In addition to the above parameters, the HV111 will
shutdown if the temperature on the die reaches ~135°C and
it will not restart until the temperature drops to 100°C or less
(could be significantly less). The thermal sensor is key in
providing a bullet proof power management solution
because it ensures that the device will turn off long before
damage can occur. This is a significant advantage over
solutions that do not contain an integral MOSFET as then
the temperature cannot be easily sensed quickly and
accurately.
Thermal engineering using the HV111 is key to proper
system operation. The 1Ω MOSFET pass element may
reach a value as high as 1.5Ω at high temperatures. There
are numerous methods to reduce the thermal resistance of
the R
θ
JA
. The following table describes some options:
Method
FR4
FR4 Heat Sink
FR4 + H/S
IMS (40cm )
IMS* w/ H/S
* IMS is a metal substrate board
2
Auto-Retry
Any fault condition will cause an automatic 9sec retry to
occur. This retry will occur indefinitely (as long as the
thermal supervisor is satisfied). Figure 6 shows typical
waveforms for the auto-retry.
PWRGD
I
DS
200ma/div
V
PP
-V
NN
50V/div
R
θ
JA
70-80° C/W
40° C/W
13° C/W
9° C/W
4.5° C/W
Description
Straight Convection
10cm PCB H/S
External Sink + Holes
Floating in Air
External Heatsink
2
Timers
The timer subsystems are critical to successful operation of
the HV111. Timers are as follows:
To determine your required thermal impedance, R
θ
JA
, is quite
simple. In a parallel to Ohms law, Power x R
θ
JA
=
∆T.
Junction temperature, which is limited to 120
°
C minimum, is
Tmaxambient +
∆T.
For example, if the highest operating
ambient temperature were 55
°
C as with many networking
applications, and the current were 1.6A, then the required
thermal resistance would be calculated as follows:
Determine maximum ambient = 55
°
C.
Determine max junction temp. = 120
°
C .
Determine max operating current = 1.6A.
Therefore
∆T
= 120-55
°
C = 65
°
C.
2
2
Max. Power = 1.23A *1.5Ω = 3.84W.
1
Timer
Power-on-Reset
Initial Inrush Timeout
2
Shorted Inrush PWM
Shorted Circuit Timer
Second Inrush (Diode
‘OR’ing):
❒
Return to Limit
❒
Timeout
Auto-Retry
1
Duration
1
4.5ms
75ms
10µs
75ms
10µs
(100µs)
3
75ms
9sec
Now
∆T
/ Power = R
θ
JA
= 65
°
/3.84W = 20
°
C/W.
To achieve a R
θ
JA
of 20
°
C/W or better the table above shows
that it will be necessary to use a DPAK external heatsink or
IMS substrate.
1
This is the time from satisfying the undervoltage comparator. Each “bounce” will reset this
timer & therefore observed delay may be higher than this “ideal” delay.
2
Shorted-circuit timer starts after POR timer. If V
DS
drops more than ¼(V
PP
-V
NN
) after t
SC
then a shorted-circuit condition exists.
3
Limit within 10µs, but may take up to 100µs to settle.
This is the minimum value of the low to high thermal shutdown according to the electrical
specifications on pg. 2.
2
This is the maximum MOSFET on resistance at high temperature.
Current Sensing – No R
SENSE
Required
The HV111 uses an internal 6000:1 current mirror to
eliminate the need for a sense resistor. This saves energy
and eliminates the need for a power component. The current
mirror used by Supertex is unique in that it utilizes special
circuitry to normalize for the variations in V
DS
between the
primary pass element and the internal element which would
otherwise cause current mismatch – and forces competitors
to use internal sense resistors in similar applications. This
mechanism also provides the shorted circuit PWM
functionality which can help protect systems in the case of
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