NCN49599
Product Preview
Power Line Communication
Modem
The NCN49599 is a powerful spread frequency shift keying
(S−FSK) communication system−on−chip (SoC) designed for
communication in hostile environments.
It combines a low power ARM Cortex M0 processor with a high
precision analogue front end and a robust line driver. Based on 4800
baud S−FSK dual−channel technology, it offers an ideal compromise
between speed and robustness.
It is functionally compatible with the NCN49597 and NCS5651
chip set, offering frequencies to cover all CENELEC bands for use in
applications such as e−metering, home automation and street lighting.
The NCN49599 benefits for more than 10 years of field experience in
e−metering and delivers innovative features such as a smart
synchronization and in−band statistics.
Fully reprogrammable, the modem firmware can be updated in the
field. Multiple royalty−free firmware options are available from
ON Semiconductor; refer to the separate datasheets for details. The
configurable GPIOs allow connecting peripherals such as LCDs or
metering ICs.
Features
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1 56
QFN56 8x8, 0.5P
CASE 485CN
MARKING DIAGRAMS
56
1
ON
ARM
NCN49599
0C599−001
AWLYYWWG
e
3
•
Power Line Communication (PLC) Modem for 50 Hz, 60 Hz and DC
Mains
A
= Assembly Location
•
Embedded Highly Linear 2−stage Power Amplifier with Current
WL
= Wafer Lot Traceability
YYWW = Date Code
Limitation, Thermal Protection, Enable/Shutdown Control,
G
= Green Designator
Rail−to−rail Drop of only
±1
V at I
out
= 1.5 A
•
Embedded ARM Cortex M0 Processor
•
8 General−purpose IOs Controllable by Software
ORDERING INFORMATION
See detailed ordering and shipping information in the package
•
Embedded 32 kB RAM; Embedded 2 kB ROM
dimensions section on page 33 of this data sheet.
•
Hardware Compliant with CENELEC EN 50065−1 and EN 50065−7
•
Half Duplex S−FSK Channel, Data Rate Selectable:
300 – 600 – 1200 – 2400 – 4800 baud (@ 50 Hz);
360 – 720 – 1440 – 2880 – 5760 baud (@ 60 Hz)
•
Programmable Carrier Frequencies in CENELEC A, B,
•
Complete Handling of Protocol Layers (physical,
C and D Band
MAC, LLC)
•
UART for Interfacing with an Application
•
Repetition Boosting Robustness and Range of the
Microcontroller
Communication (IEC firmware)
•
Power Supply 3.3 V and 12 V
Typical Applications
•
Wide Junction Temperature Range: −40°C to +125°C
•
AMR: Remote Automated Meter Reading
•
Building Automation
Available Firmware Options
•
IEC − Fully IEC61334−5−1, IEC 61334−4−32 and
•
Solar Power Control and Monitoring
Linky Compliant
•
Street Light Control and Monitoring
•
ON PL110 − Mesh Networking with Collision
•
Transmission of Alerts (fire, gas leak, water leak)
Avoidance and Error Correction
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2015 − Rev. P3
Publication Order Number:
NCN49599/D
NCN49599
APPLICATION
Application Example
JTAG
Interface
3V3_D
R
19
C
19
C
18
C
17
C
16
TXD/PRES
+12
D
7
3V3_A
3V3_D
Meter
Interface
VDD
VCC
ENB
VDDA
VDD
R
2
C
3
C
2
C
1
TX_OUT
TX_ENB
U
1
12, 13, 14, 20
15, 16
26
27
TXD
RXD
BR0
BR1
3V3_D
R
3
R
1
41 39
49
53
43
6
25
R
18
C
5
+12
+12
R
4
R
12
C
4
R
14
R
13
C
10
D
2
R
9
+12
R
7
R
8
C
6
A−
51
R
5
R
6
A_OUT
B−
52
1
54, 55
50
2
35
34
37
D
1
Application
mController
B_OUT
A+
B+
RESB
C
11
Tr
1
NCN49599
38
30
29
TEST
R
10
RX_OUT
SDO
SDI
SCK
CSB
SEN
1:2
D
3
MAINS
D
4
R
11
REF_OUT
C
9
C
7
C
8
RX_IN
45
46
28
31
Optional
External
Flash
47
33
8, 9, 10, 11,
17, 18, 36
4
RLIM
ILIM
3V3_D
ALC_IN
3V3_A
D
5
R
15
42
48
ZC_IN
GPIO bus
5
23
VDD1V8
44
VSSA
7
VSS
24
VSS
3
VEE
56
VEE
21
XIN
Y
1
22
XOUT
19
EXT_CLK_EN
C
12
R
16
R
17
C
13
C
14
C
15
D
6
Figure 1. Typical Application for the NCN49599 S−FSK Modem
Figure 1 shows an S−FSK PLC modem built around the
NCN49599. The design is a good starting point for a
CENELEC. EN 50065−1−compliant system; for further
information refer to the design manual in [1].
This design is not galvanically isolated; safety must be
considered when interfacing to a microcontroller or a PC.
For synchronization the mains is coupled in via a 1 MW
resistor; the Schottky diode pair D
5
clamps the voltage
within the input range of the zero crossing detector.
In the receive path a 2
nd
order high pass filter blocks the
mains frequency. The corner point − defined by C
7
, C
8
, R
10
and R
11
− is designed at 10 kHz. In the transmit path a 3
rd
order low pass filter built around the internal power
operational amplifier suppresses the 2
nd
and 3
rd
harmonics
to be in line with the CENELEC EN50065−1 specification.
The filter components are tuned for a space and mark
frequency of 63.3 and 74 kHz respectively, typically for
e−metering in the CENELEC A−band. The output of the
amplifier is coupled via a DC blocking capacitor C
10
to a 2:1
transformer Tr1. The high voltage capacitor C
11
couples the
secondary of this transformer to the mains. High−energetic
transients from the mains are clamped by the protection
diode combination D
3
, D
4
, together with D
1
, D
2
.
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NCN49599
Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION
Component
C
1
C
2
C
3
C
4
C
5
C
6
, C
16
, C
17
, C
18
, C
19
C
7
, C
8
C
9
, C
13
C
10
C
11
C
12
C
14
, C
15
R
1
R
2
R
3
, R
9
,
R
7
, R
8
R
12,
R
13
R
18,
R
19
R
4
R
5
R
6
R
10
R
11
R
14
R
15
R
16
R
17
D
1
, D
2
D
3
, D
4
D
5
D
6
D
7
Y
1
Tr
1
U
1
Function and Remarks
TX_OUT signal coupling
Low pass transmit filter
Low pass transmit filter
Low pass transmit filter
Low pass transmit filter
Supply decoupling
High pass receive filter
Internal 1.8 V supply decoupling; ceramic
Transmission signal coupling; 1 A rms ripple @ 70 kHz
High Voltage coupling; 630 VDC
Zero Cross noise suppression
Crystal load capacitor
Low pass receive filter
Low pass receive filter
Low pass transmit and high pass receive filter;
Amplifier bias
Receive mode input bias
Pull up
Low pass transmit filter
Low pass transmit filter
Low pass transmit filter
High pass receive filter
High pass receive filter
Line transients protection; 0.5 W
Zero crossing coupling
Current protection
ILIM LED bias
High−current Schottky clamp diodes
Unidirectional TVS
Dual low−current Schottky clamp diode
ILIM LED indication (optional)
TVS
Crystall
2:1 signal transformer
PLC modem
NCN49599
Value
470
470
68
3
2.7
100
1
10
10
220
100
36
3.3
8.2
10
10
10
10
3
1
1.6
15
30
0.47
1
5
3.3
MBRA430
P6SMB6.8AT3G
BAS70−04
LED
1SMA12CA
48 MHz
50 ppm
Tolerance
±20%
±10%
±10%
±10%
±10%
−20 +80%
±10%
−20 +80%
±20%
±20%
±20%
±20%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±5%
±1%
±5%
Unit
nF
pF
pF
pF
nF
nF
nF
mF
mF
nF
pF
pF
kW
kW
kW
kW
kW
kW
kW
kW
kW
kW
kW
W
MW
kW
kW
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NCN49599
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
POWER SUPPLY PINS VCC, VDD, VDD2, VDDA, VSS, VSSA
Absolute maximum power amplifier supply
Absolute maximum digital amplifier power supply
Absolute maximum digital modem power supply
Absolute maximum analog power supply
Absolute maximum difference between digital and analog power supply
Absolute maximum difference between digital and analog ground
Absolute maximum difference between digital and power ground
CLOCK PINS XIN, XOUT
Absolute maximum input for the clock input pin (Note 1)
Absolute maximum voltage at the clock output pin (Note 1)
V
XIN_ABSM18
V
XOUT_ABSM18
V
SS
− 0.2
V
SS
− 0.2
V
DD18
+ 0.2
V
DD18
+ 0.2
V
V
V
CC_ABSM
V
DD_ABSM
V
DD_ABSM
V
DDA_ABSM
V
DD
− V
DDA_ABSM
V
SS
− V
SSA_ABSM
V
SS
− V
EE_ABSM
V
EE
− 0.3
V
SS
− 0.3
V
SS
− 0.3
V
SSA
− 0.3
−0.1
−0.1
−0.5
13.2
3.9
3.9
3.9
0.1
0.1
0.5
V
V
V
V
V
V
V
Symbol
Min
Max
Unit
NON 5 V SAFE PINS: TX_OUT, ALC_IN, RX_IN, RX_OUT, REF_OUT, ZC_IN, TDO, SCK, SDO, SCB
Absolute maximum input for normal digital inputs and analog inputs
Absolute maximum voltage at any output pin
Maximum peak input current at the zerocrossing input pin
Maximum average input current at the zerocrossing input pin (1 ms)
V
N5VSIN_ABSM
V
N5VSOUT_ABSM
Imp
ZC_IN
Imavg
ZC_IN
V
SS
− 0.3
V
SS
− 0.3
−20
−2
V
DD
+ 0.3
V
DD
+ 0.3
20
2
V
V
mA
mA
5 V SAFE PINS: TX_ENB, TXD, RXD, BR0, BR1, IO0..IO9, RESB, TDI, TCK, TMS, TRSTB, TEST, SDI
Absolute maximum input for digital 5 V safe pins configured as input (Note 2)
Absolute maximum voltage at 5V safe pin configured as output (Note 2)
AMPLIFIER PINS A+, A−, B+, B−, BOUT1, BOUT2, VWARN, XOUT
Absolute maximum voltage at the analog amplifier pins
Absolute maximum voltage at the amplifier control pins
V
AMPA_ABSM
V
AMPC_ABSM
V
SS
− 0.3
V
SS
− 0.3
V
DD18
+ 0.3
V
CC
+ 0.3
V
V
V
5VSIN_ABSM
V
5VSOUT_ABSM
V
SS
− 0.3
V
SS
− 0.3
5.5
V
DD
+ 0.3
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The upper maximum voltage rating on the clock pins XIN and XOUT is specified with respect to the output voltage of the internal core voltage
regulator. The tolerance of this voltage regulator must be taken into account. In case an external clock is used, care must be taken not to
damage the XIN pin.
2. The direction (input or output) of configurable pins (IO0...IO9) depends on the firmware.
Normal Operating Conditions
Operating ranges define the limits for functional
operation and parametric characteristics of the device as
described in the Electrical Characteristics section and for the
reliability specifications.
Table 3. OPERATING RANGES
Rating
Power supply voltage range (VDDA and VDD pins)
Power supply voltage range (VCC pin)
Junction Temperature Range
Ambient Temperature Range
Total cumulative dwell time outside the normal power
supply voltage range or the ambient temperature under bias,
must be less than 0.1 percent of the useful life.
Symbol
V
DD
, V
DDA
Vcc
T
J
T
A
Min
3.0
6.0
−40
−40
Max
3.6
12.0
125
85
Unit
V
V
°C
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCN49599
Pin Description − QFN Package
VSSA
RX_OUT
RX_IN
REF_OUT
ZC_IN
EN
A+
A−
A_OUT
VCC
B_OUT1
B_OUT2
VEE
56
55
54
53
52
51
50
49
48
47
46
45
44
VDDA
43
B−
B+
VEE
RLIM
ILIM
VDD
VSS
IO3
IO4
IO5
IO0
TDO
TDI
TCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
17
28
42
41
40
39
38
37
NCN49599
36
35
34
33
32
31
30
29
ALC_IN
TX_OUT
NC
TX_EN
TEST
RES
IO1
BR0
BR1
SEN
IO2
CSB
SDO
SDI
Figure 2. QFN Pin−out of NCN49599 (top view)
Table 4. NCN49599 QFN PIN FUNCTION DESCRIPTION
Pin Number
1
2
3, 56
4
5
6, 25
7, 24
8..10, 17, 18
11, 36
12
13
14
15
16
19
20
21
22
Pin Name
B−
B+
VEE
RLIM
ILIM
VDD
VSS
IO3...IO7
IO0, IO1
TDO
TDI
TCK
TMS
TRSTB
EXT_CLK_EN
TXD/PRES
XIN
XOUT
In
In/Out
In/Out
Out
In
In
In
In
In
Out
In
Out
In
In
I/O
In
In
Type
A
A
P
A
A
P
P
D, 5VS, ST
D, 5VS, ST
D
D, 5VS, PD, ST
D, 5VS, PD
D, 5VS, PD
D, 5VS, PD, ST
D, 5VS, PD, ST
D, 5VS
A, 1.8V
A, 1.8V
Description
Inverting input of operational amplifier B
Non−inverting input of operational amplifier B
Negative power supply amplifiers
Amplifier B current limit set resistor pin
Current limit flag
3.3 V digital supply
Digital ground
General−purpose I/O’s (Note 3)
General−purpose I/O’s (Notes 3 and 4)
JTAG test data output (Note 5)
JTAG test data input (Note 5)
JTAG test clock (Note 5)
JTAG test mode select (Note 5)
JTAG test reset (active low)
External clock enable input
Output of transmitted data (TXD) or PRE_SLOT signal (PRES)
Crystal oscillator input
Crystal oscillator output (output must be left floating when XIN is
driven by external clock)
3. The direction and function of the general−purpose I/O’s is controlled by the firmware. Depending on the firmware behavior, a general− purpose
IO (GPIO) used as an output may appear as an open−drain, push−pull or open−source pin. Refer to the firmware documentation for details.
4. During boot (i.e., before firmware has been uploaded) this pin is an output and indicates the status of the boot loader. Once firmware has
been loaded, the pin is available as a GPIO.
5. During normal operation, this pin must be tied to ground (recommended) or left open.
6. If the modem is not loading the firmware from an external SPI memory, it is recommended that this pin is tied to ground or Vdd.
7. During normal operation, it is recommended that this pin is tied to ground.
8. During normal operation, this pin must be tied to Vdd.
9. If a general purpose IO is configured as an output, the pull−down resistor is disconnected.
SCK
RXD
TXD
VDD
VSS
VDD1V8
XOUT
XIN
TXD/PRES
EXT_CLK_EN
IO7
IO6
TRST
TMS
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