CD4033BMS
December 1992
CMOS Decade Counter/Divider
Description
CD4033BMS consists of a 5 stage Johnson decade counter
and an output decoder which converts the Johnson code to a 7
segment decoded output for driving one stage in a numerical
display.
This device is particularly advantageous in display applications
where low power dissipation and/or low package count is
important.
A high RESET signal clears the decade counter to its zero
count. The counter is advanced one count at the positive clock
signal transition if the CLOCK INHIBIT signal is low. Counter
advancement via the clock line is inhibited when the CLOCK
INHIBIT signal is high. The CLOCK INHIBIT signal can be used
as a negative-edge clock if the clock line is held high. Antilock
gating is provided on the JOHNSON counter, thus assuring
proper counting sequence. The CARRY-OUT (Cout) signal
completes one cycle every ten CLOCK INPUT cycles and is
used to clock the succeeding decade directly in a multi-decade
counting chain.
The seven decoded outputs (a, b, c, d, e, f, g) illuminate the
proper segments in a seven segment display device used for
representing the decimal numbers 0 to 9. The 7 segment out-
puts go high on selection.
Features
• High Voltage Types (20V Rating)
• Decoded 7 Segment Display Outputs and Ripple
Blanking
• Counter and 7 Segment Decoding in One Package
• Easily Interfaced with 7 Segment Display Types
• Fully Static Counter Operation DC to 6MHz (typ.) at VDD =
10V
• Ideal for Low-Power Displays
• “Ripple Blanking” and Lamp Test
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Schmitt-Triggered Clock Inputs
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Device’s
Applications
• Decade Counting 7 Segment Decimal Display
• Frequency Division 7 Segment Decimal Displays
• Clocks, Watches, Timers (e.g.
÷
60,
÷
60,
÷12
Counter/
Display
• Counter/Display Driver For Meter Applications
Pinout
CD4033BMS
TOP VIEW
Functional Diagram
VDD
16
1
CLOCK 1
CLOCK INHIBIT 2
16 VDD
15 RESET
14 LAMP TEST
13 c
12 b
11 e
10 a
9 d
3
RIPPLE
BLK
IN
8
VSS
LAMP
TEST
RESET
14
CLOCK
INHIBIT
15
CLOCK
2
10 a
12 b
13 c
9 d
11 e
6
f
7 DECODED OUTPUTS
RIPPLE BLANKING IN 3
RIPPLE BLANKING OUT 4
CARRY OUT 5
f 6
g 7
VSS 8
7 g
5
CARRY OUT
4
RIPPLE
BLK
OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3301
7-826
CD4033BMS
The CD4033BMS has provisions for automatic blanking of
the non-significant zeros in a multi-digit decimal number
which results in an easily readable display consistent with
normal writing practice. For example, the number 0050.0700
in an eight digit display would be displayed as 50.07. Zero
suppression on the integer side is obtained by connecting
the RBI terminal of the CD4033BMS associated with the
most significant digit in the display to a low-level voltage and
connecting the RBO terminal of that stage to the RBI termi-
nal of the CD4033BMS in the next-lower significant position
in the display. This procedure is continued for each succeed-
ing CD4033BMS on the interger side of the display.
On the fraction side of the display the RBI of the
CD4033BMS associated with the least significant bit is con-
nected to a low-level voltage and the RBO of that
CD4033BMS is connected to the RBI terminal of the
CD4033BMS in the next more-significant-bit position. Again,
this procedure is continued for all CD4033BMS’s on the frac-
tion side of the display.
In a purely fractional number the zero immediately preceding
the decimal point can be displayed by connecting the RBI of
that stage to a high level voltage (instead of to the RBO of
the next more-significant-stage). For example: optional zero
→
0.7346. Likewise, the zero in a number such as 763.0 can
be displayed by connecting the RBI of the CD4033BMS
associated with it to a high-level voltage.
Ripple blanking of non-significant zeros provides an appre-
ciable savings in display power.
The CD4033BMS has a LAMP TEST input which, when con-
nected to a high-level voltage, overrides normal decoder
operation and enables a check to be made on possible dis-
play malfunctions by putting the seven outputs in the high
state.
The CD4033BMS are supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H2R
H6W
Logic Diagram
*
LAMP TEST
14
COUT
(CLOCK
5
D Q
CL
CL
Q
R
D Q
CL
CL
Q
R
D Q
CL
CL
Q
R
÷
10)
15
*
D Q
CL
CL
Q
R
D Q
CL
CL
Q
R
10
a
RESET
12
b
13
c
9
d
1
CL
6
f
11
e
*
CLOCK
*
CLOCK
INHIBIT 2
7
g
3
4
16
VDD
8
GND
VDD
a
f
e
VSS
d
g
b
c
SEGMENT
DESIGNATIONS
RBO
*
RBI
*
ALL INPUTS PROTECTED
BY CMOS INPUT
PROTECTION NETWORK
FIGURE 1. CD4033BMS
7-827
Specifications CD4033BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
±
1/32 Inch (1.59mm
±
0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θ
ja
θ
jc
Ceramic DIP and FRIT Package . . . . . 80
o
C/W
20
o
C/W
Flatpack Package . . . . . . . . . . . . . . . . 70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For TA = -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For TA = +100
o
C to +125
o
C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1
2
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
3
1
2
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
3
1
2
VDD = 18V
Output Voltage
Output Voltage
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
VOL15
VOH15
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VNTH
VPTH
F
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
VIL
VIH
VIL
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
3
1, 2, 3
1, 2, 3
1
1
1
1
1
1
1
1
1
7
7
8A
8B
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
LIMITS
TEMPERATURE
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
MIN
-
-
-
-100
-1000
-100
-
-
-
-
MAX
10
1000
10
-
-
-
100
1000
100
50
-
-
-
-
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
UNITS
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
mA
mA
mA
mA
mA
mA
mA
V
V
V
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
(NOTE 1)
VDD = 20V, VIN = VDD or GND
+25
o
C, +125
o
C, -55
o
C 14.95
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
-
3.5
-
11
0.53
1.4
3.5
-
-
-
-
-2.8
0.7
VOH > VOL <
VDD/2 VDD/2
1.5
-
4
-
V
V
V
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
7-828
Specifications CD4033BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS TEMPERATURE
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
TPHL4
TPLH4
TTHL
TTLH
FCL
VDD = 5V, VIN = VDD or GND
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
LIMITS
MIN
-
-
-
-
-
-
-
-
-
-
2.5
1.85
MAX
500
675
700
945
550
743
600
810
200
270
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
PARAMETER
Propagation Delay
Clock To Carry Out
Propagation Delay
Clock To Decode Out
Propagation Delay
Reset To Carry Out
Propagation Delay
Reset To Decode Out
Transition Time
SYMBOL
TPHL1
TPLH1
TPHL2
TPLH2
TPLH3
CONDITIONS
(NOTE 1, 2)
VDD = 5V, VIN = VDD or GND
Maximum Clock Input
Frequency
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
NOTES
1, 2
TEMPERATURE
-55
o
C, +25
o
C
+125
o
C
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+125
o
C
-55
o
C
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
+125
o
C
-55
o
C
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
+125
o
C
-55
o
C
-
4.95
9.95
0.36
0.64
0.9
1.6
2.4
4.2
-
-
-
-
-
-
50
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-2.6
mV
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
MIN
-
-
-
-
-
-
-
MAX
5
150
10
300
10
600
50
UNITS
µA
µA
µA
µA
µA
µA
mV
7-829
Specifications CD4033BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
LIMITS
PARAMETER
Output Current (Source)
SYMBOL
IOH15
CONDITIONS
VDD =15V, VOUT = 13.5V
NOTES
1, 2
TEMPERATURE
+125
o
C
-55
o
C
Input Voltage Low
Input Voltage High
Propagation Delay
Clock To Carry Out
Propagation Delay
Clock To Decode Out
Propagation Delay
Reset To Carry Out
Propagation Delay
Reset To Decode Out
Transition Time
VIL
VIH
TPHL1
TPLH1
TPHL2
TPLH2
TPLH3
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
TPHL4
TPLH4
TTHL
TTLH
FCL
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
TW
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Reset Removal
Time
TREM
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Clock Pulse
Width
TW
VDD = 5V
VDD = 10V
VDD = 15V
Input Capacitance
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
SYMBOL
IDD
VNTH
∆VTN
VTP
∆VTP
F
CONDITIONS
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
NOTES
1, 4
1, 4
1, 4
1, 4
1, 4
1
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-2.8
-
0.2
-
VOH >
VDD/2
MAX
25
-0.2
±1
2.8
±1
VOL <
VDD/2
UNITS
µA
V
V
V
V
V
CIN
Any Input
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-
-
+7
-
-
-
-
-
-
-
-
-
-
5.5
8
-
-
-
-
-
-
-
-
-
-
MAX
-2.4
-4.2
3
-
200
150
250
180
240
160
250
180
100
50
-
-
120
100
50
30
15
10
220
100
80
7
UNITS
mA
mA
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Maximum Clock Input
Frequency
Minimum Reset Pulse
Width
7-830
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