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IDT71V546S100PFGI8

产品描述ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
产品类别存储    存储   
文件大小183KB,共21页
制造商IDT (Integrated Device Technology)
标准
下载文档 详细参数 选型对比 全文预览

IDT71V546S100PFGI8概述

ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100

IDT71V546S100PFGI8规格参数

参数名称属性值
是否无铅不含铅
是否Rohs认证符合
厂商名称IDT (Integrated Device Technology)
零件包装代码QFP
包装说明LQFP, QFP100,.63X.87
针数100
Reach Compliance Codecompliant
ECCN代码3A991.B.2.A
最长访问时间5 ns
其他特性PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)100 MHz
I/O 类型COMMON
JESD-30 代码R-PQFP-G100
JESD-609代码e3
长度20 mm
内存密度4718592 bit
内存集成电路类型ZBT SRAM
内存宽度36
湿度敏感等级3
功能数量1
端子数量100
字数131072 words
字数代码128000
工作模式SYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织128KX36
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码LQFP
封装等效代码QFP100,.63X.87
封装形状RECTANGULAR
封装形式FLATPACK, LOW PROFILE
并行/串行PARALLEL
峰值回流温度(摄氏度)260
电源3.3 V
认证状态Not Qualified
座面最大高度1.6 mm
最大待机电流0.045 A
最小待机电流3.14 V
最大压摆率0.26 mA
最大供电电压 (Vsup)3.465 V
最小供电电压 (Vsup)3.135 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Matte Tin (Sn) - annealed
端子形式GULL WING
端子节距0.65 mm
端子位置QUAD
处于峰值回流温度下的最长时间30
宽度14 mm
Base Number Matches1

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128K x 36, 3.3V Synchronous
IDT71V546S/XS
SRAM with ZBT™ Feature,
Burst Counter and Pipelined Outputs
Features
128K x 36 memory configuration, pipelined outputs
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized registered outputs eliminate the
need to control
OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
Packaged in a JEDEC standard 100-pin TQFP package
clock cycle, and two cycles later its associated data cycle occurs, be it
read or write.
The IDT71V546 contains data I/O, address and control signal regis-
ters. Output enable is the only asynchronous signal and can be used to
disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V546 to be
suspended as long as necessary. All synchronous inputs are ignored
when
CEN
is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three is not active
when ADV/LD is low, no new memory operation can be initiated and any
burst that was in progress is stopped. However, any pending data
transfers (reads or writes) will be completed. The data bus will tri-state two
cycles after the chip is deselected or a write initiated.
The IDT71V546 has an on-chip burst counter. In the burst mode, the
IDT71V546 can provide four cycles of data for a single address presented
to the SRAM. The order of the burst sequence is defined by the
LBO
input
pin. The
LBO
pin selects between linear and interleaved burst sequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V546 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC standard 14mm x
20mm 100- pin thin plastic quad flatpack (TQFP) for high board density.
Description
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to
eliminate dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Thus it has been given the name ZBT
TM
,
or Zero Bus Turn-around.
Address and control signals are applied to the SRAM during one
Pin Description Summary
A
0
- A
16
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
I/O
0
- I/O
31
, I/O
P1
- I/O
P4
V
DD
V
SS
Address Inputs
Three Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance Burst Address / Load New Address
Linear / Interleaved Burst Order
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
3821 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
OCTOBER 2008
DSC-3821/05
1
©2007 Integrated Device Technology, Inc.

IDT71V546S100PFGI8相似产品对比

IDT71V546S100PFGI8 IDT71V546S100PFG8 IDT71V546S133PFGI8 IDT71V546S100PFGI IDT71V546S133PFG IDT71V546S100PFG IDT71V546S133PFGI IDT71V546S133PFG8
描述 ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100 ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100 ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100 ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100 ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100 ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100 ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100 ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
是否无铅 不含铅 不含铅 不含铅 不含铅 不含铅 不含铅 不含铅 不含铅
是否Rohs认证 符合 符合 符合 符合 符合 符合 符合 符合
厂商名称 IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
零件包装代码 QFP QFP QFP QFP QFP QFP QFP QFP
包装说明 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87
针数 100 100 100 100 100 100 100 100
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant
ECCN代码 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
最长访问时间 5 ns 5 ns 4.2 ns 5 ns 4.2 ns 5 ns 4.2 ns 4.2 ns
最大时钟频率 (fCLK) 100 MHz 100 MHz 133 MHz 100 MHz 133 MHz 100 MHz 133 MHz 133 MHz
I/O 类型 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 代码 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100
JESD-609代码 e3 e3 e3 e3 e3 e3 e3 e3
长度 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm
内存密度 4718592 bit 4718592 bit 4718592 bit 4718592 bit 4718592 bit 4718592 bit 4718592 bit 4718592 bit
内存集成电路类型 ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM
内存宽度 36 36 36 36 36 36 36 36
湿度敏感等级 3 3 3 3 3 3 3 3
功能数量 1 1 1 1 1 1 1 1
端子数量 100 100 100 100 100 100 100 100
字数 131072 words 131072 words 131072 words 131072 words 131072 words 131072 words 131072 words 131072 words
字数代码 128000 128000 128000 128000 128000 128000 128000 128000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 85 °C 70 °C 85 °C 85 °C 70 °C 70 °C 85 °C 70 °C
组织 128KX36 128KX36 128KX36 128KX36 128KX36 128KX36 128KX36 128KX36
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP
封装等效代码 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
峰值回流温度(摄氏度) 260 260 260 260 260 260 260 260
电源 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm
最大待机电流 0.045 A 0.04 A 0.045 A 0.045 A 0.04 A 0.04 A 0.045 A 0.04 A
最小待机电流 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V
最大压摆率 0.26 mA 0.25 mA 0.31 mA 0.26 mA 0.3 mA 0.25 mA 0.31 mA 0.3 mA
最大供电电压 (Vsup) 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V
最小供电电压 (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL
端子面层 Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm
端子位置 QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD
处于峰值回流温度下的最长时间 30 30 30 30 30 30 30 30
宽度 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm
Base Number Matches 1 1 1 1 1 1 1 1
其他特性 PIPELINED ARCHITECTURE - PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE -
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