PSoC
®
4: PSoC 4100S
Family Datasheet
Programmable System-on-Chip (PSoC)
General Description
PSoC
®
4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM
®
Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
The PSoC 4100S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard
communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4100S products will
be upward compatible with members of the PSoC 4 platform for new applications and design needs.
Features
32-bit MCU Subsystem
■
■
■
Serial Communication
■
48-MHz ARM Cortex-M0+ CPU
Up to 64 KB of flash with Read Accelerator
Up to 8 KB of SRAM
Three independent run-time reconfigurable Serial
Communication Blocks (SCBs) with re-configurable I
2
C, SPI,
or UART functionality
Programmable Analog
■
Timing and Pulse-Width Modulation
■
■
■
Two opamps with reconfigurable high-drive external and
high-bandwidth internal drive and Comparator modes and ADC
input buffering capability. Opamps can operate in Deep Sleep
low-power mode.
12-bit 1-Msps SAR ADC with differential and single-ended
modes, and Channel Sequencer with signal averaging
Single-slope 10-bit ADC function provided by a capacitance
sensing block
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
Two low-power comparators that operate in Deep Sleep
low-power mode
Five 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
Center-aligned, Edge, and Pseudo-random modes
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
■
■
■
■
Up to 36 Programmable GPIO Pins
■
■
■
48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and
35-ball WLCSP packages
Any GPIO pin can be CapSense, analog, or digital
Drive modes, strengths, and slew rates are programmable
Programmable Digital
■
PSoC Creator Design Environment
■
Programmable logic blocks allowing Boolean operations to be
performed on port inputs and outputs
Deep Sleep mode with operational analog and 2.5-
A digital
system current
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
Low-Power 1.71-V to 5.5-V Operation
■
■
Industry-Standard Tool Compatibility
■
Capacitive Sensing
■
■
■
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) (>5:1) and water tolerance
Cypress-supplied software component makes capacitive
sensing design easy
Automatic hardware tuning (SmartSense™)
After schematic entry, development can be done with
ARM-based industry-standard development tools
LCD Drive Capability
■
LCD segment drive capability on GPIOs
Cypress Semiconductor Corporation
Document Number: 002-00122 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 26, 2017
PSoC
®
4: PSoC 4100S
Family Datasheet
Contents
Functional Definition........................................................ 4
CPU and Memory Subsystem ..................................... 4
System Resources ...................................................... 4
Analog Blocks.............................................................. 5
Fixed Function Digital.................................................. 5
GPIO ........................................................................... 6
Special Function Peripherals....................................... 6
Pinouts .............................................................................. 7
Alternate Pin Functions ............................................... 9
Power............................................................................... 11
Mode 1: 1.8 V to 5.5 V External Supply .................... 11
Mode 2: 1.8 V ±5% External Supply.......................... 11
Development Support .................................................... 12
Documentation .......................................................... 12
Online ........................................................................ 12
Tools.......................................................................... 12
Electrical Specifications ................................................ 13
Absolute Maximum Ratings....................................... 13
Device Level Specifications....................................... 13
Analog Peripherals .................................................... 17
Digital Peripherals .....................................................
Memory .....................................................................
System Resources ....................................................
Ordering Information......................................................
Packaging........................................................................
Package Diagrams ....................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Revision History .............................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
25
28
28
31
34
35
38
40
40
41
42
42
42
42
42
42
Document Number: 002-00122 Rev. *I
Page 2 of 41
PSoC
®
4: PSoC 4100S
Family Datasheet
Figure 1. Block Diagram
PSoC 4100S
Architecture
32-bit
AHB- Lite
CPU Subsystem
SWD/TC
SPCIF
Cortex
M0+
48 MHz
FAST MUL
NVIC, IRQMUX
FLASH
64 KB
Read Accelerator
SRAM
8 KB
SRAM Controller
ROM
8 KB
ROM Controller
System Resources
Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
Clock
Clock Control
WDT
ILO
IMO
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
Analog DFT
System Interconnect (Single Layer AHB)
Peripherals
PCLK
Peripheral Interconnect (MMIO)
Programmable
Analog
3x SCB
-I2C/SPI/UART
IOSS GPIO
(5x ports)
x1
SARMUX
CTBm
x1
2x Opamp
High Speed I/O Matrix & 2 x Programmable I/O
Power Modes
Active/ Sleep
DeepSleep
36x GPIOs, LCD
I/O Subsystem
PSoC 4100S devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4100S devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4100S family provides a level of security not
possible with multi-chip application solutions or with
microcontrollers. It has the following advantages:
■
■
■
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4100S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4100S allows the
customer to make.
Allows disabling of debug features
Robust flash protection
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-00122 Rev. *I
WCO
SAR ADC
(12-bit)
2x LP Comparator
5x TCPWM
CapSense
Page 3 of 41
PSoC
®
4: PSoC 4100S
Family Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0+ CPU in the PSoC 4100S is part of the 32-bit
MCU subsystem, which is optimized for low-power operation
with extensive clock gating. Most instructions are 16 bits in length
and the CPU executes a subset of the Thumb-2 instruction set.
It includes a nested vectored interrupt controller (NVIC) block
with eight interrupt inputs and also includes a Wakeup Interrupt
Controller (WIC). The WIC can wake the processor from Deep
Sleep mode, allowing power to be switched off to the main
processor when the chip is in Deep Sleep mode.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG. The debug
configuration used for PSoC 4100S has four breakpoint
(address) comparators and two watchpoint (data) comparators.
Flash
The PSoC 4100S device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The low-power flash block is
designed to deliver two wait-state (WS) access time at 48 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average.
SRAM
Eight KB of SRAM are provided with zero wait-state access at
48 MHz.
SROM
An 8 KB supervisory ROM that contains boot and configuration
routines is provided.
between different clock sources without glitching. In addition, the
clock system ensures that there are no metastable conditions.
The clock system for the PSoC 4100S consists of the internal
main oscillator (IMO), internal low-frequency oscillator (ILO), a
32 kHz Watch Crystal Oscillator (WCO) and provision for an
external clock. Clock dividers are provided to generate clocks for
peripherals on a fine-grained basis. Fractional dividers are also
provided to enable clocking of higher data rates for UARTs.
Figure 2. PSoC 4100S MCU Clocking Architecture
IMO
Divide By
2,4,8
HFCLK
External Clock
ILO
LFCLK
HFCLK
Prescaler
Integer
Dividers
Fractional
Dividers
SYSCLK
6X 16-bit
2X 16.5-bit
The HFCLK signal can be divided down to generate
synchronous clocks for the analog and digital peripherals. There
are eight clock dividers for the PSoC 4100S; two of those are
fractional dividers. The 16-bit capability allows flexible
generation of fine-grained frequency values and is fully
supported in PSoC Creator
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4100S. It is trimmed during testing to achieve the specified
accuracy.The IMO default frequency is 24 MHz and it can be
adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance
with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low power, nominally 40-kHz oscillator, which
is primarily used to generate clocks for the watchdog timer
(WDT) and peripheral operation in Deep Sleep mode. ILO-driven
counters can be calibrated to the IMO to improve accuracy.
Cypress provides a software component, which does the
calibration.
Watch Crystal Oscillator (WCO)
The PSoC 4100S clock subsystem also implements a
low-frequency (32-kHz watch crystal) oscillator that can be used
for precision timing applications.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
System Resources
Power System
The power system is described in detail in the section
Power on
page 11.
It provides assurance that voltage levels are as required
for each respective mode and either delays mode entry (for
example, on power-on reset (POR)) until voltage levels are as
required for proper functionality, or generates resets (for
example, on brown-out detection). The PSoC 4100S operates
with a single external supply over the range of either 1.8 V ±5%
(externally regulated) or 1.8 to 5.5 V (internally regulated) and
has three different power modes, transitions between which are
managed by the power system. The PSoC 4100S provides
Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with
instantaneous wake-up on a wake-up event. In Deep Sleep
mode, the high-speed clock and associated circuitry is switched
off; wake-up from this mode takes 35 µs. The opamps can
remain operational in Deep Sleep mode.
Clock System
The PSoC 4100S clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
Document Number: 002-00122 Rev. *I
Page 4 of 41
PSoC
®
4: PSoC 4100S
Family Datasheet
Reset
The PSoC 4100S can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the reset. An XRES pin is
reserved for external reset by asserting it active low. The XRES
pin has an internal pull-up resistor that is always enabled.
Buffers, Filters, Trans-Impedance Amplifiers, and other functions
can be realized, in some cases with external passives. saving
power, cost, and space. The on-chip opamps are designed with
enough bandwidth to drive the Sample-and-Hold circuit of the
ADC without requiring external buffering.
Low-power Comparators (LPC)
The PSoC 4100S has a pair of low-power comparators, which
can also operate in Deep Sleep modes. This allows the analog
system blocks to be disabled while retaining the ability to monitor
external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
where the system wake-up circuit is activated by a comparator
switch event. The LPC outputs can be routed to pins.
Current DACs
The PSoC 4100S has two IDACs, which can drive any of the pins
on the chip. These IDACs have programmable current ranges.
Analog Multiplexed Buses
The PSoC 4100S has two concentric independent buses that go
around the periphery of the chip. These buses (called amux
buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on the I/O Ports.
Analog Blocks
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion.
The Sample-and-Hold (S/H) aperture is programmable allowing
the gain bandwidth requirements of the amplifier driving the SAR
inputs, which determine its settling time, to be relaxed if required.
It is possible to provide an external bypass (through a fixed pin
location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through selected channels
autonomously (sequencer scan) with zero switching overhead
(that is, aggregate sampling bandwidth is equal to 1 Msps
whether it is for a single channel or distributed over several
channels). The sequencer switching is effected through a state
machine or through firmware driven switching. A feature
provided by the sequencer is buffering of each channel to reduce
CPU interrupt service requirements. To accommodate signals
with varying source impedance and frequency, it is possible to
have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers
(low and high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
The SAR is not available in Deep Sleep mode as it requires a
high-speed clock (up to 18 MHz). The SAR operating range is
1.71 V to 5.5 V.
Figure 3. SAR ADC
AHB System Bus and Programmable Logic
Interconnect
Programmable Digital Blocks
The Programmable I/O (Smart I/O) block is a fabric of switches
and LUTs that allows Boolean functions to be performed in
signals being routed to the pins of a GPIO port. The Smart I/O
can perform logical operations on input pins to the chip and on
signals going out as outputs.
Fixed Function Digital
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention. There are five TCPWM blocks
in the PSoC 4100S.
Serial Communication Block (SCB)
The PSoC 4100S has three serial communication blocks, which
can be programmed to have SPI, I2C, or UART functionality.
I
2
C Mode:
The hardware I
2
C block implements a full
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
400 kbps (Fast Mode) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
Page 5 of 41
SAR Sequencer
Sequencing
and Control
vminus vplus
POS
Data and
Status Flags
SARADC
NEG
SARMUX Port
(Up to 16 inputs)
SARMUX
Reference
Selection
VDDA /2
VDDA
VREF
External
Reference and
Bypass
(optional)
Inputs from other Ports
Two Opamps (Continuous-Time Block; CTB)
The PSoC 4100S has two opamps with Comparator modes
which allow most common analog functions to be performed
on-chip eliminating external components; PGAs, Voltage
Document Number: 002-00122 Rev. *I
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