UTRON
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L2568 is a 2,097,152-bit high speed
CMOS static random access memory organized as
262,144 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT62L2568 is designed for high speed system
applications. It is particularly well suited for battery
back-up nonvolatile memory applications.
The UT62L2568 operates from a single 2.7V~3.6V
power supply and all inputs and outputs are fully
TTL compatible.
UT62L2568
FEATURES
Access time:55ns(max) for Vcc=3.0V~3.6V
70/100ns(max) for Vcc=2.7V~3.6V
CMOS Low operating power
Operating : 45/35/25mA (Icc max)
Standby : 20µA (TYP.) L-version
3µA (TYP.) LL-version
Single 2.7V~3.6V power supply
Operating Temperature:
Commercial : 0
℃
~70
℃
Extended : -20
℃
~80
℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min)
Package : 32 pin 8mm×20 mm TSOP-I
32 pin 8mm×13.4mm STSOP
36 pin 6mm×8mmTFBGA
PIN DESCRIPTION
SYMBOL
A0 - A17
I/O1 - I/O8
CE1 ,CE2
WE
OE
Vcc
Vss
NC
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A8
A13
A14
A15
A16
A17
I/O1
I/O8
CE 1
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable 1,2 Input
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
.
ROW
DECODER
MEMORY ARRAY
2048 ROWS × 128 COLUMNS × 8bits
VCC
VSS
.
.
.
.
.
.
I/O
CONTROL
.
.
.
.
.
.
.
.
COLUMN I/O
COLUMN DECODER
CE2
WE
LOGIC
CONTROL
A9 A10 A11 A12 A5 A6
A7
OE
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80059
1
UTRON
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
UT62L2568
PIN CONFIGURATION
A11
A9
A8
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
OE
A
B
C
D
E
F
G
H
A0
I/O5
I/O6
Vss
Vcc
I/O7
I/O8
A9
A1
A2
CE2
A3
A4
A6
A7
A8
I/O1
I/O2
Vcc
Vss
CE1
UT62L2568
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
WE
NC
A5
NC
A17
A16
A12
A15
A13
I/O3
I/O4
A14
OE
CE
1
A10 A11
TSOP-1/STSOP
1
2
3
TFBGA
4
5
6
TRUTH TABLE
MODE
Standby
Standby
Output Disable
Read
Write
Note:
CE
1
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O OPERATION
High - Z
High -Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
,
I
SB1
I
SB
,
I
SB1
I
CC
I
CC
I
CC
H = V
IH
, L=V
IL
, X = Don't care.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80059
2
UTRON
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
UT62L2568
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Commercial
Operating Temperature
Extended
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
SYMBOL
V
TERM
T
A
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 4.6
0 to 70
-20 to 80
-65 to 150
1
50
260
UNIT
V
℃
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V, TA =0
℃
to 70
℃
/ -20
℃
to 80
℃
(E))
PARAMETER
SYMBOL
TEST CONDITION
Power Voltage
Vcc
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input Leakage Current
I
LI
V
SS
≦
V
IN
≦
V
CC
Output Leakage Current
I
LO
V
SS
≦
V
I/O
≦
V
CC,
Output Disabled
Output High Voltage
V
OH
I
OH
= - 1mA
Output Low Voltage
V
OL
I
OL
= 2mA
Operating Power
I
CC
Cycle time=Min.100% duty,
55
Supply Current
CE
1
=V
IL
, CE2 = V
IH
, I
I/O
=0mA , 70
100
Icc1 Cycle time = 1µs,100% duty,
CE
1
≦
0.2V,CE2
≧
V
CC
-0.2V,
I
I/O=
0mA,
other pins at 0.2V or Vcc-0.2V,
Cycle time =500ns,100% duty,
CE
1
≦
0.2V,CE2
≧
V
CC
-0.2V,
I
I/O=
0mA,
other pins at 0.2V or Vcc-0.2V,
CE
1
=V
IH
or CE2 = V
IL
-L
CE
1
≧
V
CC
-0.2V or
.CE2
≦
0.2V,
other pins at 0.2V or Vcc-0.2V, -LL
MIN. TYP.
2.7
3.0
2.0
-
- 0.2
-
-1
-
-1
-
2.2
-
-
-
-
30
-
25
-
20
-
4
MAX.
3.6
Vcc+0.3
0.6
1
1
-
0.4
45
35
25
5
UNIT
V
V
V
µA
µA
V
V
mA
mA
mA
mA
Icc2
-
8
10
mA
Standby Current(TTL)
Standby Current(CMOS)
I
SB1
I
SB1
-
-
-
0.3
20
3
0.5
80
25
mA
µA
µA
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80059
3
UTRON
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
UT62L2568
CAPACITANCE
(TA=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 30pF, I
OH
/I
OL
= -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V , TA =0
℃
to 70
℃
/ -20
℃
to 80
℃
(E))
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
SYMBOL
UT62L2568-55*
UT62L2568-70
UT62L2568-100
UNIT
t
RC
t
AA
t
ACE1,
t
ACE2
t
OE
t
CLZ1*,
t
CLZ2*
t
OLZ*
t
CHZ1*,
t
CHZ2*
t
OHZ*
t
OH
MIN.
55
-
-
-
10
5
-
-
5
MAX.
-
55
55
30
-
-
20
20
-
MIN.
70
-
-
-
10
5
-
-
5
MAX.
-
70
70
35
-
-
25
25
-
MIN.
100
-
-
-
10
5
-
-
5
MAX.
-
100
100
50
-
-
30
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
SYMBOL
UT62L2568-55*
UT62L2568-70
UT62L2568-100
UNIT
t
WC
t
AW
t
CW1,
t
CW2
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
MIN.
55
50
50
0
45
0
25
0
5
-
MAX.
-
-
-
-
-
-
-
-
-
30
MIN.
70
60
60
0
55
0
30
0
5
-
MAX.
-
-
-
-
-
-
-
-
-
30
MIN.
100
80
80
0
70
0
40
0
5
-
MAX.
-
-
-
-
-
-
-
-
-
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
*55ns for Vcc=3.0V~3.6V
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80059
4
UTRON
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
UT62L2568
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
tR
C
Address
t
AA
t
OH
t
OH
DOUT
Data Valid
READ CYCLE 2
(
CE
and
OE
Controlled)
(1,3,5,6)
t
RC
Address
t
AA
CE1
t
ACE1
CE2
t
ACE2
OE
t
CLZ1
t
CLZ2
Dout
HIGH-Z
t
OE
t
OH
Data Valid
t
OHZ
t
CHZ1
t
CHZ2
HIGH-Z
t
OLZ
Notes :
WE
is HIGH for read cycle.
2. Device is continuously selected
CE
1
=V
IL
and CE2=V
IH.
1.
3. Address must be valid prior to or coincident with
CE
1
and CE2 transition; otherwise t
AA
is the limiting parameter.
4.
OE
is low.
5. t
CLZ1
, t
CLZ2
, t
OLZ
, t
CHZ1
, t
CHZ2
and t
OHZ
are specified with C
L
=5pF. Transition is measured
±500mV
from steady state.
6. At any given temperature and voltage condition, t
CHZ1
is less than t
CLZ1
, t
CHZ2
is less than t
CLZ2
, t
OHZ
is less than t
OLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80059
5
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