schemes, such as internal temperature compensation, ensure
that the CY2DP3110 delivers consistent performance over
various platforms
Block Diagram
V
BB
Pin Configuration
Q1
Q1#
VCC
CLKA
CLKA#
Q2
Q2#
VEE
VCC
CLKB
CLKB#
Q3
Q3#
Q4
Q4#
VCC
CLK_SEL
CLKA
CLKA#
VBB
CLKB
CLKB#
VEE
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
VCC
Q0
Q0#
Q1
Q1#
Q2
Q2#
VCC
Q0
Q0#
CY2DP3110
CLK_SEL
VEE
VBB
Q7
Q7#
Q8
Q8#
Q9
Q9#
Cypress Semiconductor Corporation
Document #: 38-07469 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 18, 2005
VCC
Q9#
Q9
Q8#
Q8
Q7#
Q7
VCC
Q6
Q6#
9
10
11
12
13
14
15
16
VEE
Q5
Q5#
24
23
22
21
20
19
18
17
Q3
Q3#
Q4
Q4#
Q5
Q5#
Q6
Q6#
FastEdge™ Series
CY2DP3110
Pin Definitions
[1, 2, 3]
Pin
2
3
4
5
6
7
8
1,9,16,
25,32
31,29,27,24,22,20,18,
15,13,11
30,28,26,23,21,19,17,
14,12,10
Table 1.
Control
CLK_SEL
0
1
CLKA, CLKA# input pair is active (Default condition with no connection to pin)
CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations
CLKB, CLKB# input pair is active.
CLKB can be driven with HSTL compatible signals with respective power configurations
Operation
Name
CLK_SEL
CLKA
CLKA#
VBB
CLKB,
CLKB#
VEE
VCC
Q(0:9)
Q#(0:9)
I/O
I,PD
I,PD
[1]
O
I,PD
I,PD/PU
–PWR
+PWR
O
O
Type
ECL/PECL
Input Clock Select.
ECL/PECL
Differential Input Clocks.
Bias
HSTL
HSTL
Power
Power
Reference Voltage Output.
Alternate Differential Input Clocks.
Alternate Differential Input Clocks.
Negative Power Supply.
Positive Power Supply.
Description
I,PD/PU ECL/PECL
Differential Input Clocks.
ECL/PECL
ECL/PECL Differential Output Clocks.
ECL/PECL
ECL/PECL Differential Output Clocks.
Governing Agencies
The following agencies provide specifications that apply to the
CY2DP3110. The agency name and relevant specification is
listed below in
Table 2.
Table 2.
Agency Name
JEDEC
Specification
JESD 020B (MSL)
JESD 8-6 (HSTL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
883E Method 1012.1 (Thermal Theta JC)
Mil-Spec
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power.
2. In ECL mode (negative power supply mode), V
EE
is either –3.3V or –2.5V and V
CC
is connected to GND (0V). In PECL mode (positive power supply mode),
V
EE
is connected to GND (0V) and V
CC
is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (V
CC
)
and are between V
CC
and V
EE
.
3. V
BB
is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).
Document #: 38-07469 Rev. *I
Page 2 of 10
FastEdge™ Series
CY2DP3110
Absolute Maximum Ratings
Parameter
V
CC
V
EE
T
S
T
J
ESD
h
M
SL
Description
Positive Supply Voltage
Negative Supply Voltage
Temperature, Storage
Temperature, Junction
ESD Protection
Moisture Sensitivity Level
Assembled Die
Condition
Non-Functional
Non-Functional
Non-Functional
Non-Functional
Human Body Model
2000
3
50
Min.
–0.3
-4.6
–65
Max.
4.6
0.3
+150
150
Unit
V
V
°C
°C
V
N.A.
gates
Gate Count Total Number of Used Gates
Multiple Supplies:
The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Operating Conditions
Parameter
I
BB
LU
I
T
A
Ø
Jc
Ø
Ja
I
EE
C
IN
L
IN
V
IN
V
TT
V
OUT
I
IN
Description
Output Reference Current
Latch Up Immunity
Temperature, Operating Ambient
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Maximum Quiescent Supply Current
Input pin capacitance
Pin Inductance
Input Voltage
Output Termination Voltage
Output Voltage
Input
Current
[7]
Relative to V
CC[6]
Relative to V
CC[6]
Relative to V
CC
[6]
Condition
Relative to V
BB
Functional, typical
Functional
Functional
Functional
V
EE
pin
Min.
100
–40
35
[4]
76
[4]
Max.
|200|
+85
Unit
uA
mA
°C
°C/W
°C/W
130
[5]
3
1
–0.3
–0.3
V
CC
+ 0.3
V
CC
– 2
V
CC
+ 0.3
l150l
mA
pF
nH
V
V
V
uA
V
IN
= V
IL
, or V
IN
= V
IH
PECL/HSTL DC Electrical Specifications
Parameter
V
CC
V
CMR
V
X
V
OH
V
OL
V
IH
V
IL
V
BB[3]
Description
Operating Voltage
PECL Input Differential Cross Point
Voltage
[8]
Condition
2.5V ± 5%, V
EE
= 0.0V
3.3V ± 5%, V
EE
= 0.0V
Differential operation
Min.
2.375
3.135
1.2
0.68
V
CC
– 1.25
V
CC
– 1.995
V
CC
–1.995
V
CC
– 1.165
V
CC
–
1.945
[11]
V
CC
– 1.620
Max.
2.625
3.465
V
CC
0.9
V
CC
– 0.7
V
CC
– 1.5
V
CC
– 1.3
V
CC
– 0.880
[11]
V
CC
– 1.625
V
CC
– 1.220
Unit
V
V
V
V
V
V
V
V
V
V
HSTL Input Differential Crosspoint Volt- Standard Load Differential
age
[9]
Operation
Output High Voltage
Output Low Voltage
V
CC
= 3.3V ± 5%
V
CC
= 2.5V ± 5%
Input Voltage, High
Input Voltage, Low
Output Reference Voltage
I
OH
= –30 mA
[10]
I
OL
= –5
mA
[10]
Single-ended operation
Single-ended operation
Relative to V
CC[6]
Notes:
4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1
5. Power Calculation: V
CC
* I
EE
+0.5 (I
OH
+ I
OL
) (V
OH
– V
OL
) (number of differential outputs used); I
EE
does not include current going off chip.
6. where V
CC
is 3.3V±5% or 2.5V±5%.
7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current.
8. Refer to
Figure 1.
9. V
X
(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the V
X
(AC) range and the input
swing lies within the V
DIF
(AC) specification. Violation of V
X
(AC) or V
DIF
(AC) impacts the device propagation delay, device and part-to-part skew. Refer to
Figure 2.
10. Equivalent to a termination of 50Ω to VTT. I
OHMIN
=(V
OHMIN
– V
TT
)/50; I
OHMAX
=(V
OHMAX
– V
TT
)/50; I
OLMIN
=(V
OLMIN
– V
TT
)/50; I
OLMAX
=(V
OLMAX
– V
TT
)/50.
11. V
IL
will operate down to V
EE
; V
IH
will operate up to V
CC
.
Document #: 38-07469 Rev. *I
Page 3 of 10
FastEdge™ Series
CY2DP3110
ECL DC Electrical Specifications
Parameter
V
EE
V
CMR
V
OH
V
OL
V
IH
V
IL
V
BB[3]
Description
Negative Power Supply
ECL Input Differential Cross Point
Voltage
[8]
Output High Voltage
Output Low Voltage
V
EE
= –3.3V ± 5%
V
EE
= –2.5V ± 5%
Input Voltage, High
Input Voltage, Low
Output Reference Voltage
Condition
–2.5V ± 5%, V
CC
= 0.0V
–3.3V ± 5%, V
CC
= 0.0V
Differential operation
I
OH
= –30 mA
[10]
I
OL
= –5
mA
[10]
Min.
–2.625
–3.465
V
EE
+ 1.2
–1.25
–1.995
–1.995
–1.165
–1.945
[11]
–1.620
Max.
–2.375
–3.135
0V
–0.7
–1.5
–1.3
–0.880
[11]
–1.625
–1.220
Unit
V
V
V
V
V
V
V
Single-ended operation
Single-ended operation
AC Electrical Specifications
Parameter
V
PP
V
CMRO
F
CLK
T
PD
V
DIF
V
O
tsk
(O)
tsk
(PP)
t
jit(per)
t
jit(pn)
Description
PECL/ECL Differential Input Voltage
[8]
Output Common Voltage Range (typ.)
Input Frequency
Propagation Delay CLKA or CLKB to
Output pair
[13]
HSTL Differential Input Voltage
[12]
Output Voltage
(peak-to-peak; see
Figure 2)
Output-to-output Skew
Part-to-Part Output
Output Period Jitter
Skew
[13]
(peak)
[14]
156.25
MHz
[13]
156.25 MHz, 3.3V, broadband
156.25 MHz, 3.3V, filtered
312.5 MHz, 3.3V, broadband
312.5 MHz, 3.3V, filtered
tsk
(P)
T
R
,T
F
Output Pulse
Skew
[15]
660
MHz
[13]
,
See
Figure 3
Output Rise/Fall Time (see
Figure 2)
50% duty cycle
Differential 20% to 80%
50% duty cycle Standard load
PECL, ECL < 660 MHz
HSTL < 1 GHz
Duty Cycle Standard Load
Differential Operation
< 1 GHz
<660 MHz
[13]
, See
Figure 3
–
280
280
0.4
0.375
–
–
–
–
–
–
–
–
0.08
400
400
–
–
29
95
7.2
0.165
0.151
0.141
0.107
–
–
Condition
Differential operation
Min.
0.1
V
CC
– 1.425
1.5
650
750
1.9
–
50
150
15
–
–
–
–
50
0.3
Typ.
Max.
1.3
Unit
V
V
GHz
ps
ps
V
V
ps
ps
ps
ps
ps
ps
ps
ps
ps
Output RMS Phase Jitter
[13, 14]
(See
Figure 6)
Notes:
12. V
DIF
(AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tkpd and device-to-device skew.
13. 50% duty cycle; standard load; differential operation.
14. Typical jitter measurements are taken at room temperature and nominal voltage. For further information regarding jitter, please refer to the Application note
“Understanding Data sheet Jitter Specifications for Cypress Timing Products.”
15. Output pulse skew is the absolute difference of the propagation delay times: | t
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