GS820E32AT-180/166/133/4/5
TQFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipelined opera-
tion
• Dual Cycle Deselect (DCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
64K x 32
2Mb Synchronous Burst SRAM
180 MHz–133 MHz
3.3 V V
DD
3.3 V and 2.5 V I/O
Flow Through/Pipeline Reads
The function of the Data Output Register can be controlled by
the user via the FT mode pin (Pin 14 in the TQFP). Holding
the FT mode pin low places the RAM in Flow Through mode,
causing output data to bypass the Data Output Register.
Holding FT high places the RAM in Pipelined mode,
activating the rising-edge-triggered Data Output Register.
DCD Pipelined Reads
The GS820E32A is a DCD (Dual Cycle Deselect) pipelined
synchronous SRAM. SCD (Single Cycle Deselect) versions are
also available. DCD SRAMs pipeline disable commands to the
same degree as read commands. DCD SRAMs hold the
deselect command for one full cycle and then begin turning off
their outputs just after the second rising edge of the clock.
Functional Description
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Applications
The GS820E32A is a 2,097,152-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
isc
Controls
Addresses, data I/Os, chip enables (E
1
, E
2
, E
3
), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
on
D
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Parameter Synopsis
tCycle
t
KQ
I
DD
tCycle
t
KQ
I
DD
-180
5.5 ns
3.2 ns
155 mA
9.1 ns
8 ns
100 mA
-166
6 ns
3.5 ns
140 mA
10 ns
8.5 ns
90 mA
1/20
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.08 1/2009
Pr
-133 (-4)
7.5 ns
4 ns
115 mA
12 ns
10 ns
80 mA
-5
10 ns
5 ns
90 mA
15 ns
12 ns
65 mA
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS820E32A operates on a 3.3 V power supply and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuit.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
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© 2000, GSI Technology
GS820E32AT-180/166/133/4/5
TQFP Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
NC
BW
B
A
, B
B
B
C
, B
D
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
I
I
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
I/O
Data Input and Output pins
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
tin
D
isc
Rev: 1.08 1/2009
on
ue
d
3/20
Burst address counter advance enable; active low
Sleep Mode control; active high
Address Strobe (Processor, Cache Controller); active low
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Pr
Output Enable; active low
Clock Input Signal; active high
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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No Connect
© 2000, GSI Technology
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