CAT25010, CAT25020,
CAT25040
1-Kb, 2-Kb and 4-Kb SPI
Serial CMOS EEPROM
Description
The CAT25010/20/40 are 1−Kb/2−Kb/4−Kb Serial CMOS
EEPROM devices internally organized as 128x8/256x8/512x8 bits.
They feature a 16−byte page write buffer and support the Serial
Peripheral Interface (SPI) protocol. The device is enabled through a
Chip Select (CS) input. In addition, the required bus signals are a clock
input (SCK), data input (SI) and data output (SO) lines. The HOLD
input may be used to pause any serial communication with the
CAT25010/20/40 device. These devices feature software and
hardware write protection, including partial as well as full array
protection.
Features
http://onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
MSOP−8
Z SUFFIX
CASE 846AD
TDFN−8
VP2 SUFFIX
CASE 511AK
•
•
•
•
•
•
•
•
•
•
•
•
•
10 MHz SPI Compatible
1.8 V to 5.5 V Supply Voltage Range
SPI Modes (0,0) & (1,1)
16−byte Page Write Buffer
Self−timed Write Cycle
Hardware and Software Protection
Block Write Protection
−
Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
8−lead PDIP, SOIC, TSSOP and 8−pad TDFN Packages
These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V
CC
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
CS
SO
WP
V
SS
1
V
CC
HOLD
SCK
SI
PDIP (L), SOIC (V), MSOP (Z)
TSSOP (Y), TDFN (VP2)
PIN FUNCTION
Pin Name
CS
SO
WP
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
SI
CS
WP
HOLD
SCK
V
SS
CAT25010
CAT25020
CAT25040
SO
V
SS
SI
SCK
HOLD
V
CC
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
August, 2009
−
Rev. 20
1
Publication Order Number:
CAT25010/D
CAT25010, CAT25020, CAT25040
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Operating Temperature
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
−45
to +130
−65
to +150
−0.5
to V
CC
+ 0.5
Units
°C
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
Table 3. D.C. OPERATING CHARACTERISTICS
(
V
CC
= +1.8 V to +5.5 V, T
A
=
−40°C
to +125°C unless otherwise specified.)
Symbol
I
CC
I
SB1
I
SB2
I
L
I
LO
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Supply Current
Test Conditions
Read, Write, V
CC
= 5.0 V,
SO open
V
IN
= GND or V
CC
, CS = V
CC
,
WP = V
CC
, V
CC
= 5.0 V
V
IN
= GND or V
CC
, CS = V
CC
,
WP = GND, V
CC
= 5.0 V
V
IN
= GND or V
CC
CS = V
CC
,
V
OUT
= GND or V
CC
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
−2
−1
−1
−0.5
0.7 V
CC
V
CC
> 2.5 V, I
OL
= 3.0 mA
V
CC
> 2.5 V, I
OH
=
−1.6
mA
V
CC
> 1.8 V, I
OL
= 150
mA
V
CC
> 1.8 V, I
OH
=
−100
mA
V
CC
−
0.2 V
V
CC
−
0.8 V
0.2
10 MHz /
−40°C
to 85°C
5 MHz /
−40°C
to 125°C
Min
Max
2
2
2
4
5
2
1
2
0.3 V
CC
V
CC
+ 0.5
0.4
Units
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
Standby Current
Standby Current
Input Leakage Current
Output Leakage
Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Table 4. PIN CAPACITANCE
(Note 2) (T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V)
Symbol
C
OUT
C
IN
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
Test
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
8
8
Units
pF
pF
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
http://onsemi.com
2
CAT25010, CAT25020, CAT25040
Table 5. A.C. CHARACTERISTICS
(T
A
=
−40°C
to +125°C, unless otherwise specified.) (Notes 4, 8)
V
CC
= 2.5 V
−
5.5 V
V
CC
= 1.8 V
−
5.5 V
Symbol
f
SCK
t
SU
t
H
t
WH
t
WL
t
LZ
t
RI
(Note 5)
t
FI
(Note 5)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
CNS
t
CNH
t
WPS
t
WPH
t
WC
(Note 7)
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
WP Hold Time
Write Cycle Time
50
20
30
20
20
10
100
5
0
50
100
20
15
20
15
15
10
60
5
0
10
75
0
20
25
Parameter
Min
DC
40
40
75
75
50
2
2
0
10
40
Max
5
T
A
=
−405C
to +855C
Min
DC
20
20
40
40
25
2
2
Max
10
Units
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Table 6. POWER−UP TIMING
(Notes 5, 6)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Max
1
1
Units
ms
ms
4. AC Test Conditions:
Input Pulse Voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤
10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
OL max
/I
OH max
; C
L
= 50 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
7. t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
8.
All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). t
CSH
timing specification is valid
for die revision D and higher. The die revision D is identified by letter “D” or a dedicated marking code on top of the package. For
previous product revision (Rev. C) the t
CSH
is defined relative to the negative clock edge (please refer to data sheet
Doc. No. MD-1006 Rev. U)
http://onsemi.com
3
CAT25010, CAT25020, CAT25040
Pin Description
Functional Description
SI:
The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO:
The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK:
The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25010/20/40.
CS:
The chip select input pin is used to enable/disable the
CAT25010/20/40. When CS is high, the SO output is
tri−stated (high impedance) and the device is in Standby
Mode (unless an internal write operation is in progress).
Every communication session between host and
CAT25010/20/40 must be preceded by a high to low transition
and concluded with a low to high transition of the CS input.
WP:
The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low all write operations are inhibited.
HOLD:
The HOLD input pin is used to pause transmission
between host and CAT25010/20/40, without having to
retransmit the entire sequence at a later time. To pause,
HOLD must be taken low and to resume it must be taken
back high, with the SCK input low during both transitions.
When not used for pausing, the HOLD input should be tied
to V
CC
, either directly or through a resistor.
CS
t
CNH
SCK
t
SU
SI
t
H
VALID
IN
t
V
t
HO
SO
HI−Z
VALID
OUT
t
RI
t
FI
t
CSS
t
WH
t
WL
The CAT25010/20/40 devices support the Serial
Peripheral Interface (SPI) bus protocol, modes (0,0) and
(1,1). The device contains an 8−bit instruction register. The
instruction set and associated op−codes are listed in Table 7.
Reading data stored in the CAT25010/20/40 is
accomplished by simply providing the READ command and
an address. Writing to the CAT25010/20/40, in addition to
a WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits in
a Status Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAT25010/20/40 will accept any one of the six instruction
op−codes listed in Table 7 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
Table 7. INSTRUCTION SET
(Note 9)
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
0000 X010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
9. X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
t
CS
t
CSH
t
CNS
t
V
t
DIS
HI−Z
Figure 2. Synchronous Data Timing
Status Register
The Status Register, as shown in Table 8, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
http://onsemi.com
4
CAT25010, CAT25020, CAT25040
Table 8. STATUS REGISTER
7
1
6
1
5
1
4
1
3
BP1
2
BP0
1
WEL
0
RDY
Table 9. BLOCK PROTECTION BITS
Status Register Bits
BP1
0
0
1
1
BP0
0
1
0
1
None
CAT25010: 060−07F, CAT25020: 0C0−0FF, CAT25040: 180−1FF
CAT25010: 040−07F, CAT25020: 080−0FF, CAT25040: 100−1FF
CAT25010: 000−07F, CAT25020: 000−0FF, CAT25040: 000−1FF
Array Address Protected
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
WRITE OPERATIONS
The CAT25010/20/40 device powers up into a write
instruction to the CAT25010/20/40. Care must be taken to
disable state. The device contains a Write Enable Latch
take the CS input high after the WREN instruction, as
(WEL) which must be set before attempting to write to the
otherwise the Write Enable Latch will not be properly set.
memory array or to the status register. In addition, the
WREN timing is illustrated in Figure 3. The WREN
address of the memory location(s) to be written must be
instruction must be sent prior to any WRITE or WRSR
outside the protected area, as defined by BP0 and BP1 bits
instruction.
from the status register.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
Write Enable and Write Disable
operations by resetting the WEL bit, will protect the device
The internal Write Enable Latch and the corresponding
against inadvertent writes.
Status Register WEL bit are set by sending the WREN
CS
SCK
SI
0
0
0
0
0
1
1
0
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
Figure 3. WREN Timing
CS
SCK
SI
0
0
0
0
0
1
0
0
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
Figure 4. WRDI Timing
http://onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
