Ratio of Third Overtone Mode ESR to Ratio used because typical R
1
values are much
Fundamental Mode ESR
less than the maximum spec
Crystal Drive Level
No external series resistor assumed
Operating Conditions
Parameter
V
DD
T
A
C
LOAD
F
ref
Supply Voltage
Ambient Commercial Temperature
Ambient Industrial Temperature
Max. Load Capacitance at pin 6 and pin 7
External Reference Crystal
(Fundamental tuned crystals only)
External Reference Clock
F
SSCLK
F
REFCLK
F
MOD
T
PU
SSCLK output frequency, C
LOAD
= 15 pF
REFCLK output frequency, C
LOAD
= 15 pF
Spread Spectrum Modulation Frequency
Power up time for all VDDs to reach minimum specified voltage (power ramp must be
monotonic)
Description
Min
3.13
0
–40
–
8
8
3
8
30.0
0.05
Typ.
3.30
–
–
–
–
–
–
–
31.5
–
Max
3.45
70
85
15
30
166
200
166
33.0
500
Unit
V
°C
°C
pF
MHz
MHz
MHz
MHz
kHz
ms
DC Electrical Characteristics
Parameter
I
OH
I
OL
V
IH
V
IL
I
IH
I
IL
I
OZ
C
XIN
or
C
XOUT[1]
C
IN
[1]
Description
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Input High Current, PD#/OE and
SSON# pins
Condition
V
OH
= V
DD
– 0.5, V
DD
= 3.3V (source)
V
OL
= 0.5, V
DD
= 3.3V (sink)
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
V
in
= V
DD
Min
10
10
0.7V
DD
–
–
–
–10
–
–
–
Typ.
12
12
–
–
–
–
Max
Unit
mA
mA
V
DD
0.3V
D
D
V
V
μA
μA
μA
pF
pF
pF
10
10
10
Input Low Current, PD#/OE and SSON# V
in
= V
SS
pins
Output Leakage Current
Programmable Capacitance at pin 2
and pin 3
Input Capacitance at pin 4 and pin 8
Three-state output, PD#/OE = 0
Capacitance at minimum setting
Capacitance at maximum setting
Input pins excluding XIN and XOUT
12
60
5
–
–
7
Note
1. Guaranteed by characterization, not 100% tested.
Document #: 38-07499 Rev. *E
Page 4 of 13
[+] Feedback
CY25100
DC Electrical Characteristics
Parameter
I
VDD
I
DDS
(continued)
Condition
V
DD
= 3.45V, Fin = 30 MHz,
REFCLK = 30 MHz, SSCLK = 66 MHz,
C
LOAD
= 15 pF, PD#/OE = SSON# = V
DD
V
DD
= 3.45V, Device powered down with
PD# = 0V (driven reference pulled down)
Description
Supply Current
Min
–
Typ.
25
Max
35
Unit
mA
μA
Standby current
–
15
30
AC Electrical Characteristics
[1]
Parameter
DC
Description
Output Duty Cycle
Output Duty Cycle
SR1
SR2
SR3
SR4
T
CCJ1[2]
Rising Edge Slew Rate
Falling Edge Slew Rate
Rising Edge Slew Rate
Falling Edge Slew Rate
Cycle-to-Cycle Jitter
SSCLK (Pin 7)
Condition
SSCLK, Measured at V
DD
/2
REFCLK, Measured at V
DD
/2
Duty Cycle of CLKIN = 50% at input bias
SSCLK from 3 to 100 MHz; REFCLK from 3 to
100 MHz. 20%–80% of V
DD
SSCLK from 3 to 100 MHz; REFCLK from 3 to
100 MHz. 80%–20% of V
DD
SSCLK from 100 to 200 MHz; REFCLK from 100
to 166 MHz 20%–80% of V
DD
SSCLK from 100 to 200 MHz; REFCLK from 100
to 166 MHz 80%–20% of V
DD
CLKIN = SSCLK = 166 MHz, 2% spread,
REFCLK off
CLKIN = SSCLK = 66 MHz, 2% spread,
REFCLK off
CLKIN = SSCLK = 33 MHz, 2% spread,
REFCLK off
T
CCJ2[2]
Cycle-to-Cycle Jitter
SSCLK (Pin 7)
CLKIN = SSCLK = 166 MHz, 2% spread,
REFCLK on
CLKIN = SSCLK = 66 MHz, 2% spread,
REFCLK on
CLKIN = SSCLK = 33 MHz, 2% spread,
REFCLK on
T
CCJ3[2]
Cycle-to-Cycle Jitter
REFCLK (Pin 6)
CLKIN = SSCLK = 166 MHz, 2% spread,
REFCLK on
CLKIN = SSCLK = 66 MHz, 2% spread,
REFCLK on
CLKIN = SSCLK = 33 MHz, 2% spread,
REFCLK on
t
STP
T
OE1
T
OE2
Power down Time
(pin 4 = PD#)
Output Disable Time
(pin 4 = OE)
Output Enable Time
(pin 4 = OE)
Time from falling edge on PD# to stopped
outputs (Asynchronous)
Time from falling edge on OE to stopped outputs
(Asynchronous)
Time from rising edge on OE to outputs at a valid
frequency (Asynchronous)
Min
45
40
0.7
0.7
1.2
1.2
–
–
–
–
–
–
–
–
–
–
–
–
Typ.
50
50
1.1
1.1
1.6
1.6
90
100
130
100
105
200
80
100
135
150
150
150
Max
55
60
3.6
3.6
4.0
4.0
120
130
170
130
140
260
100
130
180
350
350
350
Unit
%
%
V/ns
V/ns
V/ns
V/ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
Notes
2. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, spread percentage, temperature,
and output load. For more information, refer to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at
http://www.cypress.com/clock/appnotes.html,
or contact your local Cypress Field Application Engineer.
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