SN55LVDS33-SP
www.ti.com
SGLS393 – MARCH 2008
HIGH-SPEED DIFFERENTIAL RECEIVER
1
FEATURES
400-Mbps Signaling Rate and 200-Mxfr/s Data
Transfer Rate
(1)
Operates With a Single 3.3-V Supply
–4 V to 5 V Common-Mode Input Voltage
Range
Differential Input Thresholds < ±50 mV With
50 mV of Hysteresis Over Entire
Common-Mode Input Voltage Range
Complies With TIA/EIA-644 (LVDS)
Active Failsafe Assures a High-Level Output
With No Input
Bus-Pin ESD Protection Exceeds 15-kV HBM
Input Remains High-Impedance On Power
Down
TTL Inputs Are 5-V Tolerant
Pin-Compatible With the AM26LS32,
SN65LVDS32B, µA9637, SN65LVDS9637B
QML-V Qualified, SMD 5962-07248
Military Temperature Range (–55°C to 125°C)
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
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SN55LVDS33W
W PACKAGE
(TOP VIEW)
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(1)
DESCRIPTION/ORDERING INFORMATION
These LVDS data line receivers offers the widest common-mode input voltage range in the industry. These
receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall
increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an
option.
Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis
to improve noise rejection on slowly changing input signals. The input thresholds are still no more than +50 mV
over the full input common-mode voltage range.
The receivers can withstand ±15-kV Human-Body Model (HBM) and ±600-V Machine Model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) failsafe circuit that provides a high-level output within 600 ns after
loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or
powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these
fault conditions. This feature may also be used for wired-OR bus signaling. See
The Active Failsafe Feature of
the SN65LVDS32B
application note.
The intended application and signaling technique of these devices is point-to-point baseband data transmission
over controlled impedance media of approximately 100
Ω.
The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media and the noise coupling to the environment.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
SN55LVDS33-SP
SGLS393 – MARCH 2008
www.ti.com
The SN55LVDS33 is characterized for operation from –55°C to 125°C.
ORDERING INFORMATION
(1)
T
A
–55°C to 125°C
(1)
(2)
CFP - W
PACKAGE
(2)
Tube
ORDERABLE PART NUMBER
5962-0724801VFA
TOP-SIDE MARKING
5962-0724801VFA
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at
www.ti.com.
Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
FUNCTION TABLE
(1)
SN55LVDS33
DIFFERENTIAL INPUT
V
ID
= V
A
– V
B
V
ID
≥
–32 mV
–100 mV < V
ID
≤
–32 mV
V
ID
≤
–100 mV
X
Open
G
H
X
H
X
H
X
L
H
X
ENABLES
G
X
L
X
L
X
L
H
X
L
OUTPUT
Y
H
H
?
?
L
L
Z
H
H
(1)
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
2
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SN55LVDS33-SP
Copyright © 2008, Texas Instruments Incorporated
SN55LVDS33-SP
www.ti.com
SGLS393 – MARCH 2008
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
Attenuation
Network
V
CC
1 pF
60 kΩ
A Input
200 kΩ
3 pF
250 kΩ
7V
7V
6.5 kΩ
6.5 kΩ
Attenuation
Network
Attenuation
Network
B Input
7V
7V
V
CC
V
CC
300 kΩ
(G Only)
100
Ω
Enable
Inputs
7V
37
Ω
Y Output
7V
300 kΩ
(G Only)
Copyright © 2008, Texas Instruments Incorporated
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3
SN55LVDS33-SP
SGLS393 – MARCH 2008
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
Supply voltage range, V
CC
Voltage range
Electrostatic discharge
Charged-device mode
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
(3)
(4)
(2)
–0.5 V to +4 V
Enables or Y
A or B
A, B, and GND
All pins
(4)
(3)
–1 V to +6 V
–5 V to +6 V
Class 3, A: 15 kV, B: 500 V
±500 V
–65°C to 150°C
260°C
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN
V
CC
V
IH
V
IL
|V
ID
|
V
I
or V
IC
T
A
Supply voltage
High-level input voltage
Low-level input voltage
Magnitude of differential input voltage
Voltage at any bus terminal (separately or common-mode)
Operating free-air temperature
Enables
Enables
3
2
0
0.1
–4
–55
NOM
3.3
MAX
3.6
5
0.8
3
5
125
UNIT
V
V
V
V
°C
4
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Copyright © 2008, Texas Instruments Incorporated
SN55LVDS33-SP
www.ti.com
SGLS393 – MARCH 2008
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
V
IT1
V
IT2
V
IT3
V
ID(HYS)
V
OH
V
OL
I
CC
Positive-going differential input voltage threshold
(2)
Negative-going differential input voltage
threshold
(2)
Differential input failsafe voltage threshold
(2)
Differential input voltage hysteresis,
V
IT1
– V
IT2
High-level output voltage
Low-level output voltage
Supply current
I
OH
= –4 mA
I
OL
= 4 mA
G at V
CC
, No load,
G at GND
V
I
= 0 V,
I
I
Input current
(A or B inputs)
V
I
= 2.4 V,
V
I
= –4 V,
V
I
= 5 V,
I
IO
I
I(OFF)
I
IH
I
IL
I
OZ
C
I
Differential input current (I
IA
– I
IB
)
Power-off input current (A or B inputs)
High-level input current (enables)
Low-level input current (enables)
High-impedance output current
Input capacitance, A or B input to GND
V
I
= 0.4 sin (4E6πt) + 0.5 V
V
ID
= 100 mV,
Other input open
Other input open
Other input open
Other input open
V
IC
= –4 V or 5 V
Steady state
16
1.1
2.4
0.4
25
6
±25
±25
±80
±45
±5
±25
±60
12
12
–10
5
12
µA
µA
µA
µA
µA
pF
µA
V
IB
= –4 V or 5 V, See
Figure 2
See
Table 1
and
Figure 5
–50
–32
50
–100
TEST CONDITIONS
MIN
TYP
(1)
MAX
50
mV
mV
V
V
V
mA
UNIT
V
A
or V
B
= 0 V or 2.4 V, V
CC
= 0 V
V
A
or V
B
= –4 or 5 V, V
CC
= 0 V
V
IH
= 2 V
V
IL
= 0.8 V
(1)
(2)
All typical values are at 25°C and with a 3.3-V supply.
Not production tested but guaranteed to the limit.
Copyright © 2008, Texas Instruments Incorporated
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SN55LVDS33-SP
5
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