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CY7C1441AV33-100BZXI: 产品描述Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165; 产品类别存储存储; 文件大小683KB，共31页; 制造商Cypress(赛普拉斯); 标准

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CY7C1441AV33-100BZXI概述

Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165

CY7C1441AV33-100BZXI规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	Cypress(赛普拉斯)
零件包装代码	BGA
包装说明	15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
针数	165
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	8.5 ns
其他特性	FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)	100 MHz
I/O 类型	COMMON
JESD-30 代码	R-PBGA-B165
JESD-609代码	e1
长度	17 mm
内存密度	37748736 bit
内存集成电路类型	CACHE SRAM
内存宽度	36
湿度敏感等级	3
功能数量	1
端子数量	165
字数	1048576 words
字数代码	1000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	1MX36
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装等效代码	BGA165,11X15,40
封装形状	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	260
电源	2.5/3.3,3.3 V
认证状态	Not Qualified
座面最大高度	1.4 mm
最小待机电流	3.14 V
最大压摆率	0.29 mA
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3.135 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	20
宽度	15 mm
Base Number Matches	1

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

36-Mbit (1M x 36/2M x 18/512K x 72)

Flow-Through SRAM

Features

■

Functional Description

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33

[1]

are

3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through

SRAMs, respectively designed to interface with high-speed

microprocessors with minimum glue logic. Maximum access

delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip

counter captures the first address in a burst and increments the

address automatically for the rest of the burst access. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

Chip Enable (CE

), depth-expansion Chip Enables (CE

and

), Burst Control inputs (ADSC, ADSP, and ADV), Write

Enables (BW

, and BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and the ZZ

pin.

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows

either interleaved or linear burst sequences, selected by the

MODE input pin. A HIGH selects an interleaved burst sequence,

while a LOW selects a linear burst sequence. Burst accesses

can be initiated with the Processor Address Strobe (ADSP) or the

cache Controller Address Strobe (ADSC) inputs. Address

advancement is controlled by the Address Advancement (ADV)

input.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

Advance pin (ADV).

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33

operates from a +3.3V core power supply while all outputs may

operate with either a +2.5 or +3.3V supply. All inputs and outputs

are JEDEC-standard JESD8-5-compatible.

Supports 133-MHz bus operations

1M x 36/2M x 18/512K x 72 common IO

3.3V core power supply

2.5V or 3.3V IO power supply

Fast clock-to-output times

❐

6.5 ns (133-MHz version)

Provide high-performance 2-1-1-1 access rate

User-selectable burst counter supporting Intel® Pentium®

interleaved or linear burst sequences

Separate processor and controller address strobes

Synchronous self-timed write

Asynchronous output enable

CY7C1441AV33, CY7C1443AV33 available in

JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and

non-lead-free 165-ball FBGA package. CY7C1447AV33

available in Pb-free and non-lead-free 209-ball FBGA package

IEEE 1149.1 JTAG-Compatible Boundary Scan

“ZZ” Sleep Mode option

■

Selection Guide

Description

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

133 MHz

6.5

310

120

100 MHz

8.5

290

120

Unit

Note

1. For best-practices recommendations, please refer to the Cypress application note

System Design Guidelines

on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05357 Rev. *G

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised May 09, 2008

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CY7C1441AV33-100BZXI相似产品对比

	CY7C1441AV33-100BZXI	CY7C1441AV33-117AXC	CY7C1441AV33-133AXCT	CY7C1441AV33-133BZXC	CY7C1441AV33-100AXI	CY7C1441AV33-100BZC	CY7C1441AV33-100BZI	CY7C1441AV33-100BZXC	CY7C1441AV33-133BZC	CY7C1441AV33-100AXC
描述	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165	sram 1mx36 3.3V sync FT sram com	IC sram 36mbit 133mhz 100lqfp	Cache SRAM, 1MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165	Cache SRAM, 1MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165	Cache SRAM, 1MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165	Cache SRAM, 1MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
是否Rohs认证	符合	-	-	符合	符合	不符合	不符合	符合	不符合	符合
厂商名称	Cypress(赛普拉斯)	Cypress(赛普拉斯)	-	Cypress(赛普拉斯)	-	-	-	Cypress(赛普拉斯)	Cypress(赛普拉斯)	Cypress(赛普拉斯)
零件包装代码	BGA	-	-	BGA	QFP	BGA	BGA	BGA	BGA	QFP
包装说明	15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165	-	-	15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165	LQFP, QFP100,.63X.87	15 X 17 MM, 1.40 MM HEIGHT, FBGA-165	15 X 17 MM, 1.40 MM HEIGHT, FBGA-165	15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165	15 X 17 MM, 1.40 MM HEIGHT, FBGA-165	LQFP, QFP100,.63X.87
针数	165	-	-	165	100	165	165	165	165	100
Reach Compliance Code	compliant	-	-	unknown	compliant	compliant	compliant	compliant	compliant	compliant
ECCN代码	3A991.B.2.A	-	-	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	8.5 ns	-	-	6.5 ns	8.5 ns	8.5 ns	8.5 ns	8.5 ns	6.5 ns	8.5 ns
其他特性	FLOW-THROUGH ARCHITECTURE	-	-	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)	100 MHz	-	-	-	100 MHz	100 MHz	100 MHz	100 MHz	133 MHz	100 MHz
I/O 类型	COMMON	-	-	-	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PBGA-B165	-	-	R-PBGA-B165	R-PQFP-G100	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PQFP-G100
JESD-609代码	e1	-	-	e1	e3	e0	e0	e1	e0	e3
长度	17 mm	-	-	17 mm	20 mm	17 mm	17 mm	17 mm	17 mm	20 mm
内存密度	37748736 bit	-	-	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit
内存集成电路类型	CACHE SRAM	-	-	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
内存宽度	36	-	-	36	36	36	36	36	36	36
湿度敏感等级	3	-	-	5	3	3	3	3	3	3
功能数量	1	-	-	1	1	1	1	1	1	1
端子数量	165	-	-	165	100	165	165	165	165	100
字数	1048576 words	-	-	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words
字数代码	1000000	-	-	1000000	1000000	1000000	1000000	1000000	1000000	1000000
工作模式	SYNCHRONOUS	-	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	-	-	70 °C	85 °C	70 °C	85 °C	70 °C	70 °C	70 °C
组织	1MX36	-	-	1MX36	1MX36	1MX36	1MX36	1MX36	1MX36	1MX36
输出特性	3-STATE	-	-	-	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LBGA	-	-	LBGA	LQFP	LBGA	LBGA	LBGA	LBGA	LQFP
封装等效代码	BGA165,11X15,40	-	-	-	QFP100,.63X.87	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	QFP100,.63X.87
封装形状	RECTANGULAR	-	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE	-	-	GRID ARRAY, LOW PROFILE	FLATPACK, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	FLATPACK, LOW PROFILE
并行/串行	PARALLEL	-	-	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	260	-	-	260	260	220	220	260	220	260
电源	2.5/3.3,3.3 V	-	-	-	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V
认证状态	Not Qualified	-	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.4 mm	-	-	1.4 mm	1.6 mm	1.4 mm	1.4 mm	1.4 mm	1.4 mm	1.6 mm
最小待机电流	3.14 V	-	-	-	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
最大压摆率	0.29 mA	-	-	-	0.29 mA	0.29 mA	0.29 mA	0.29 mA	0.31 mA	0.29 mA
最大供电电压 (Vsup)	3.6 V	-	-	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3.135 V	-	-	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
标称供电电压 (Vsup)	3.3 V	-	-	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	-	-	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	-	-	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	-	-	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)	-	-	Tin/Silver/Copper (Sn/Ag/Cu)	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead (Sn/Pb)	Matte Tin (Sn)
端子形式	BALL	-	-	BALL	GULL WING	BALL	BALL	BALL	BALL	GULL WING
端子节距	1 mm	-	-	1 mm	0.65 mm	1 mm	1 mm	1 mm	1 mm	0.65 mm
端子位置	BOTTOM	-	-	BOTTOM	QUAD	BOTTOM	BOTTOM	BOTTOM	BOTTOM	QUAD
处于峰值回流温度下的最长时间	20	-	-	20	40	NOT SPECIFIED	NOT SPECIFIED	20	NOT SPECIFIED	40
宽度	15 mm	-	-	15 mm	14 mm	15 mm	15 mm	15 mm	15 mm	14 mm

CY7C1441AV33-100BZXI

CY7C1441AV33-100BZXI概述

CY7C1441AV33-100BZXI规格参数

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