The UT54ACS164 and the UT54ACTS164 are 8-bit shift reg-
isters which feature AND-gated serial inputs and an asynchro-
nous clear. The gated serial inputs (A and B) permit complete
control over incoming data. A low at either input inhibits entry
of new data and resets the first flip-flop to the low level at the
next clock pulse. A high-level at both serial inputs sets the first
flip-flop to the high level at the next clock pulse. Data at the
serial inputs may be changed while the clock is high or low,
providing the minimum setup time requirements are met. Clock-
ing occurs on the low-to-high-level transition of the clock input.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
CLR
L
H
H
H
H
CLK
X
L
↑
↑
↑
A
X
X
H
L
X
B
X
X
H
X
L
Q
A
L
Q
A0
H
L
L
OUTPUTS
Q
B
L
Q
B0
Q
An
Q
An
Q
An
...
V
DD
Q
H
Q
G
Q
F
Q
E
CLR
CLK
B
Q
A
Q
B
Q
C
Q
D
V
SS
LOGIC SYMBOL
(9)
CLR
(8)
CLK
A
(1)
(2)
SRG8
R
C1/
&
1D
(3)
(4)
Q
H
L
Q
H0
Q
Gn
Q
Gn
Q
Gn
B
Q
A
Q
B
(5)
Q
(6)
C
Q
D
(10)
Q
(11)
E
Q
(12)
F
Q
(13)
G
Q
H
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Notes:
1. Q
A0
, Q
B0
, Q
H0
= the level of Q
A
, Q
B
or Q
H
, respectively, before the indicated
steady-state input conditions were established.
2. Q
An
and Q
Gn
= the level of Q
A
or Q
G
before the most recent
↑
transition of
the clock; indicates a one-bit shift.
1
LOGIC DIAGRAM
(9)
(8)
C
R
K
S
C
R
K
S
(3)
Q
A
Q
B
C
R
K
S
(4)
Q
C
C
R
K
S
(5)
Q
D
C
R
K
S
(6)
Q
E
C
R
K
S
(10)
Q
F
C
R
K
S
(11)
Q
G
C
R
K
S
(12)
Q
H
(13)
CLR
CLK
SERIAL
(1)
A
B (2)
2
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
3
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V
±
10%; V
SS
= 0V
6
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
V
IL
PARAMETER
Low-level input voltage
1
ACTS
ACS
High-level input voltage
1
ACTS
ACS
Input leakage current
ACTS/ACS
Low-level output voltage
3
ACTS
ACS
High-level output voltage
3
ACTS
ACS
Short-circuit output current
2 ,4
ACTS/ACS
Output current
10
(Sink)
I
OH
Output current
10
(Source)
P
total
I
DDQ
ΔI
DDQ
Power dissipation
2, 8, 9
Quiescent Supply Current
Quiescent Supply Current Delta
ACTS
V
IN
= V
DD
or V
SS
I
OL
= 8.0mA
I
OL
= 100μA
I
OH
= -8.0mA
I
OH
= -100μA
V
O
= V
DD
and V
SS
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
IN
= V
DD
or V
SS
V
OH
= V
DD
- 0.4V
C
L
= 50pF
V
DD
= 5.5V
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
15
15
pF
pF
1.9
10
1.6
mW/
MHz
μA
mA
-8
mA
.7V
DD
V
DD
- 0.25
-200
8
200
.5V
DD
.7V
DD
-1
1
CONDITION
MIN
MAX
0.8
.3V
DD
UNIT
V
V
IH
V
I
IN
V
OL
μA
0.40
0.25
V
V
OH
V
I
OS
I
OL
mA
mA
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤
5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
≤
1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
淘e淘
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
