USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C343
64-Macrocell MAX
®
EPLD
Features
• 64 MAX
®
macrocells in four LABs
• Eightdedicated inputs, 24 bidirectional I/O pins
• Programmable interconnect array
• 0.8-micron double-metal CMOS EPROM technology
• Available in 44-pin HLCC, PLCC
• Lowest power MAX device
Functional Description
The CY7C343 is a high-performance, high-density erasable
programmable logic device, available in 44-pin PLCC and
HLCC packages.
The CY7C343 contains 64 highly flexible macrocells and 128
expander product terms. These resources are divided into four
Logic Array Blocks (LABs) connected through the Program-
mable Inter-connect Array (PIA). There are eight input pins,
one that doubles as a clock pin when needed. The CY7C343
also has 28 I/O pins, each connected to a macrocell (six for
LABs A and C, and eight for LABs B and D). The remaining 36
macrocells are used for embedded logic.
The CY7C343 is excellent for a wide range of both
synchronous and asynchronous applications.
Logic Block Diagram
9 INPUT
11 INPUT
12 INPUT
13 INPUT
DEDICATED INPUTS
SYSTEM CLOCK
LAB A
2
4
5
6
7
8
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELLS 7–16
INPUT 35
INPUT/CLK 34
INPUT 33
INPUT 31
LAB D
MACROCELL 56
MACROCELL 55
MACROCELL 54
MACROCELL 53
MACROCELL 52
MACROCELL 51
MACROCELL 50
MACROCELL 49
1
44
42
41
40
39
38
37
I/O PINS
I/O PINS
LAB B
15
16
17
18
19
20
22
23
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22
MACROCELL 23
MACROCELL 24
MACROCELLS 25–32
(3, 14, 25, 36)
(10, 21, 32, 43)
P
I
A
MACROCELLS 57–64
LAB C
MACROCELL 38
MACROCELL 37
MACROCELL 36
MACROCELL 35
MACROCELL 34
MACROCELL 33
I/O PINS
30
29
28
27
26
24
I/O PINS
MACROCELLS 39–48
V
CC
GND
Selection Guide
Maximum Access Time
Maximum Operating Current
7C343-20
20
135
225
225
125
200
200
7C343-25
25
135
225
225
125
200
200
7C343-30
30
135
225
225
125
200
200
7C343-35
35
135
225
225
125
200
200
Unit
ns
mA
Maximum Standby Current
Commercial
Military
Industrial
Commercial
Military
Industrial
mA
Cypress Semiconductor Corporation
Document #: 38-03015 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised April 22, 2004
USE ULTRA37000™ FOR
ALL NEW DESIGNS
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals, which
may cause glitches in internal or external logic. The fixed
delay, regardless of programmable interconnect array config-
uration, simplifies design by ensuring that internal signal
skews or races are avoided. The result is simpler design imple-
mentation, often in a single pass, without the multiple internal
logic placement and routing iterations required for a program-
mable gate array to achieve design timing objectives.
CY7C343
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay t
EXP
to the overall delay. Similarly, there is an
additional t
PIA
delay for an input from an I/O pin when
compared to a signal from a straight input pin.
When calculating synchronous frequencies, use t
S1
if all inputs
are on the input pins. t
S2
should be used if data is applied at
an I/O pin. If t
S2
is greater than t
CO1
, 1/t
S2
becomes the limiting
frequency in the data path mode unless 1/(t
WH
+ t
WL
) is less
than 1/t
S2
.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
EXP
to t
S1
. Determine which
of 1/(t
WH
+ t
WL
), 1/t
CO1
, or 1/(t
EXP
+ t
S1
) is the lowest
frequency. The lowest of these frequencies is the maximum
data path frequency for the synchronous configuration.
When calculating external asynchronous frequencies, use
t
AS1
if all inputs are on dedicated input pins. If any data is
applied to an I/O pin, t
AS2
must be used as the required set-up
time. If (t
AS2
+ t
AH
) is greater than t
ACO1
, 1/(t
AS2
+ t
AH
)
becomes the limiting frequency in the data path mode unless
1/(t
AWH
+ t
AH
) is less than 1/(t
AS2
+ t
AH
).
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
EXP
to t
AS1
. Determine
which of 1/(t
AWH
+ t
AWL
), 1/t
ACO1
, or 1/(t
EXP
+ t
AS1
) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous configu-
ration.
The parameter t
OH
indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same synchronous
clock. If t
OH
is greater than the minimum required input hold
time of the subsequent synchronous logic, then the devices
are guaranteed to function properly with a common
synchronous clock under worst-case environmental and
supply voltage conditions.
The parameter t
AOH
indicates the system compatibility of this
device when driving subsequent registered logic with a
positive hold time and using the same clock as the CY7C343.
In general, if t
AOH
is greater than the minimum required input
hold time of the subsequent logic (synchronous or
asynchronous), then the devices are guaranteed to function
properly under worst-case environmental and supply voltage
conditions, provided the clock signal source is the same. This
also applies if expander logic is used in the clock signal path
of the driving device, but not for the driven device. This is due
to the expander logic in the second device’s clock signal path
adding an additional delay (t
EXP
), causing the output data from
the preceding device to change prior to the arrival of the clock
signal at the following device’s register.
Timing Delays
Timing delays within the CY7C343 may be easily determined
using
Warp
®
,
Warp
Professional™, or
Warp
Enterprise™
software. The CY7C343 has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this data sheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect
device reliability. The CY7C343 contains circuitry to protect
device pins from high static voltages or electric fields;
however, normal precautions should be taken to avoid
applying any voltage higher than maximum rated voltages.
For proper operation, input and output pins must be
constrained to the range GND < (V
IN
or V
OUT
) < V
CC
. Unused
inputs must always be tied to an appropriate logic level (either
V
CC
or GND). Each set of V
CC
and GND pins must be
connected together directly at the device. Power supply
decoupling capacitors of at least 0.2
µ
F must be connected
between V
CC
and GND. For the most effective decoupling,
each V
CC
pin should be separately decoupled to GND, directly
at the device. Decoupling capacitors should have good
frequency response, such as monolithic ceramic types.
Document #: 38-03015 Rev. *B
Page 3 of 19
USE ULTRA37000™ FOR
ALL NEW DESIGNS
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –65
°
C to +150
°
C
Ambient Temperature with
Power Applied.................................................. 0
°
C to +70
°
C
Maximum Junction Temperature
(Under Bias)................................................................. 150
°
C
Supply Voltage to Ground Potential ............... –2.0V to +7.0V
Maximum Power Dissipation...................................2500 mW
DC V
CC
or GND Current ............................................500 mA
Electrical Characteristics
Over the Operating Range
[3]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC1
I
CC2
t
R
t
F
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input Current
Output Leakage Current
Output Short Circuit Current
Power Supply Current (Standby)
Power Supply Current
[6]
Recommended Input Rise Time
Recommended Input Fall Time
GND < V
IN
< V
CC
V
O
= V
CC
or GND
V
CC
= Max., V
OUT
=
V
I
= V
CC
or GND
(No Load)
V
I
= V
CC
or GND (No
Load) f = 1.0 MHz
[5, 6]
0.5V
[4, 5]
Commercial
Military/Industrial
Commercial
Military/Industrial
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8 mA
2.2
–0.3
–10
–40
–30
Min.
2.4
CY7C343
DC Output Current, per Pin ......................–25 mA to +25 mA
DC Input Voltage
[1]
.........................................–3.0V to +7.0V
DC Program Voltage..................................................... 13.0V
Static Discharge Voltage........................................... > 1100V
(per MIL–STD–883, method 3015)
Operating Range
[2]
Range
Commercial
Industrial
Military
Ambient Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C (Case)
V
CC
5V
±5%
5V
±10%
5V
±10%
Max.
0.45
V
CC
+ 0.3
0.8
+10
+40
–90
125
200
135
225
100
100
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
ns
ns
Capacitance
[7]
Parameter
C
IN
C
OUT
R1 464Ω
5V
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
OUTPUT
R2
250Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
163
Ω
1.75V
Notes:
1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns.
2. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
3. Typical values are for T
A
= 25°C and V
CC
= 5V.
4. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5V has been chosen to avoid
test problems caused by tester ground degradation.
5. Guaranteed but not 100% tested.
6. Measured with device programmed as a 16-bit counter in each LAB. This parameter is tested periodically by sampling production material.
7. Part (a) in AC Test Load and Waveforms is used for all parameters except t
ER
and t
XZ
, which is used for part (b) in AC Test Load and Waveforms. All external
timing parameters are measured referenced to external pins of the device.
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 2V, f = 1.0 MHz
V
OUT
= 2.0V, f = 1.0 MHz
R1 464
Ω
Max.
10
10
Unit
pF
pF
AC Test Loads and Waveforms
[7]
ALL INPUT PULSES
3.0V
R2
250Ω
10%
GND
< 6 ns
90%
90%
10%
< 6 ns
(a)
(b)
THÉVENIN EQUIVALENT (commercial/military)
Document #: 38-03015 Rev. *B
Page 5 of 19
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
