CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
6.
θ
JA
Rated with standard PC Board,
θ
JC
rated with infinite heat sink.
Electrical Specifications
PARAMETER
Standby Current, No Load
Supply Current, Full Load
Output Clamping Voltage (Note 7)
Output Clamping Energy
Output Leakage Current 1 (Note 8)
Output Leakage Current 2 (Note 8)
Output Leakage Current 3 (Note 8)
V
CC
= 4.5V to 5.5V, T
A
= -40
o
C to 125
o
C, Unless Otherwise Specified
SYMBOL
I
CCO
I
CC
V
OC
E
OC
I
O LEAK1
I
O LEAK2
I
O LEAK3
r
DSON
C
OUT
t
d(ON)
No Load
All Outputs ON, 0.5A Load Per Output
I
LOAD
= 0.5A, Output Programmed OFF
1ms Single Pulse Width, T
A
= 25
o
C,
(Refer to Figure 4 for SOA)
V
OUT
= 25V, Outputs OFF
V
OUT
= 16V, Outputs OFF
V
OUT
= 16V, Outputs OFF, V
CC
= 1V
I
LOAD
= 0.5A; T
J
= 150
o
C
V
OUT
= 16V, f = 1MHz
R
L
= 500Ω, V
CE
= 50% to V
OUT
= 0.9 x V
BATT
,
V
IN0,1
= 50% to V
OUT
= 0.9 x V
BATT
,
V
BATT
= 16V
R
L
= 500Ω, V
CE
= 50% to V
OUT
= 0.9 x V
BATT
,
V
BATT
= 16V
R
L
= 500Ω, V
CE
= 50% to V
OUT
= 0.1 x V
BATT
,
V
IN0,1
= 50% to V
OUT
= 0.9 x V
BATT
,
V
BATT
= 16V
For V
OUT
= 90% to 30% of V
BATT;
V
BATT
= 16V,
R
L
= 500Ω
For V
OUT
= 90% to 30% of V
BATT;
V
BATT
= 16V,
R
L
= 500Ω
For V
OUT
= 30% to 90% of V
BATT;
V
BATT
= 16V,
R
L
= 500Ω
For V
OUT
= 30% to 80% of V
OC;
V
BATT
= 0.9 x V
OC
, R
L
= 500Ω
TEST CONDITIONS
MIN
-
-
45
20
-
-
-
-
-
-
TYP
-
-
-
45
-
-
-
-
-
-
MAX
5
5
62
-
100
100
10
1.5
20
5
UNITS
mA
mA
V
mJ
µA
µA
µA
Ω
pF
µs
Drain-to-Source On Resistance, OUT0 - 7
Output Capacitance
Turn-On Delay, OUT0, 1
Turn-On Delay, OUT2 - 7
Turn-Off Delay
t
d(ON)
t
d(OFF)
-
-
-
-
10
10
µs
µs
Turn-On Voltage Slew-Rate, OUT2 - 7
Turn-On Voltage Slew-Rate, OUT0, 1
Turn-Off Voltage Slew-Rate, OUT0 - 7
Turn-Off Voltage Slew-Rate, OUT0 - 7
FAULT PARAMETERS
Reverse Current Drive, OUT0 - 7
Reverse Voltage Drop, OUT0 - 7
∆I
CC
during Reverse Current Drive
dV
ON1
------------------
-
dt
dV
ON2
------------------
-
dt
dV
OFF1
---------------------
-
dt
dV
OFF2
---------------------
-
dt
-
-
-
-
0.7
2
2
2
3.5
10
10
15
V/µs
V/µs
V/µs
V/µs
I
RD
V
RD
∆I
CC
I
OUT
= -3A, t
≤2ms
I
OUT
= -3A, t
≤2ms
-500
-1.5
-
-
-
-
-
-
100
mA
V
mA
4-3
HIP0045
Electrical Specifications
PARAMETER
Open Load Threshold Voltage
Open Load Pull-Down Current
Over-Current Shutdown Threshold, OUT0 - 5
Short Circuit Current Limit, OUT6, 7
Short Circuit Shutdown Delay, OUT0 - 5
Disable Fault Detection Time, Channel IN0,
IN1 After Input Switch Transition
Over-Temperature Detection Threshold
V
CC
= 4.5V to 5.5V, T
A
= -40
o
C to 125
o
C, Unless Otherwise Specified
(Continued)
SYMBOL
V
REF
I
SK
I
SC
I
LIM
t
SC
t
DF
T
OFF
TEST CONDITIONS
Open Load Fault Condition, Fault Detected If
V
OUT
< V
REF
No Load, V
OUT
= V
BATT
= 16V
V
CC
= 5V
V
CC
= 5V
MIN
0.32 x
V
CC
20
1.05
1.05
0.2
15
155
TYP
-
-
1.4
1.4
-
-
165
MAX
0.4x
V
CC
100
2
1.75
12
50
175
UNITS
V
µA
A
A
µs
µs
o
C
LOGIC INPUTS (IN0, IN1, MOSI, SCK, RESET, CE)
Threshold Voltage at Falling Edge
Threshold Voltage at Rising Edge
Hysteresis Voltage
Input Current
Input Pull-Up Resistance
Input Capacitance
Input Frequency, IN0, IN15
Active Supply Range for Reset State
Change at RESET Pin
Low V
CC
Active Reset Threshold
LOGIC OUTPUT (MISO)
Data Output LOW Voltage
Data Output HIGH Voltage
Output Three-State Leakage Current
Output Capacitance
V
SOL
V
SOH
I
SOL
C
SO
I
SO
= -3.2mA
I
SO
= -4mA
CE = High, 0V
≤
V
SO
≤
V
CC
f
OPER
= 3MHz
-
V
CC
-
0.4V
-10
-
0.2
-
-
-
0.4
-
+10
10
V
V
µA
pF
V
T
-
V
T
+
V
H
I
IN
R
IN
C
IN
f
IN
V
HCC_RS
RESET Pin Forced Reset. (Note: Normal V
CC
Functional Operating Range is 4.0V to 5.5V)
T
V
LCC_RST
Low V
CC
Forced Reset, (Low Voltage Reset
Active for 0 < V
CC
< V
LCC_RST
)
V
T
+ - V
T
-
V
IN
= V
CC
0.2xV
CC
-
0.65
-
50
-
DC
3.1
3.1
-
-
-
-
80
-
-
-
-
-
0.7xV
CC
-
+10
200
10
2
5.5
4
V
V
V
µA
kΩ
pF
kHz
V
V
Serial Peripheral Interface Timing
PARAMETER
Clock Frequency, 50% Duty Cycle
Enable Lead Time
(SCK Change Low to High after CE = Low)
Enable Lag Time
(Time for SCK Low before CE goes High)
Minimum Time SCK = High
Minimum Time SCK = Low
(MOSI, MISO Load Capacitor = 100pF, See Figure 1)
SYMBOL
f
CLK
t
LEAD
t
LAG
t
WSCKH
t
WSCKL
t
SU
t
H
t
EN
t
DIS
-
-
TEST CONDITION
MIN
3
100
150
160
160
20
TYP
-
-
-
-
-
-
-
-
-
MAX
-
-
-
-
-
-
20
100
100
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time (SCK Change from High to Low
after MOSI Data Valid)
Data Hold Time (MOSI Data Hold Time SCK
Change from High to Low)
Enable Time from CE = Low to Data at MISO
Disable Time
(Time for CE Low to High to Output Data Float)
4-4
HIP0045
Serial Peripheral Interface Timing
PARAMETER
Data Valid Time, SCK to Data at MISO Valid
Time for SCK Low before CE Low (SCK Setup Time
before CE High to Low Change)
Time for SCK High after CE High
CE Pulse Filter Time
NOTES:
7. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns-on the MOSFET; holding the Drain at the Output
Clamp Voltage, V
OC
.
8. The measurement of Output Leakage Current includes the Output Pull-Down Current, I
SK
. Each Output has a Current Pull-Down which is used
to detect open load fault conditions.
9. The digital filter time for the output latch function determines if the output latch function will be enabled. The output latch function will only be
enabled if a positive CE slope occurs after 8 SCK clock cycles or a multiple of 8 SCK cycles since the last CE negative slope change.
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