F
eatures
•
Integer Unit Based on SPARC V7 High-performance RISC Architecture
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Optimized Integrated 32/64-bit Floating-point Unit
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On-chip Peripherals:
– EDAC and Parity Generator and Checker
– Memory Interface:
Chip Select Generator
Waitstate Generation
Memory Protection
– DMA Arbiter
– Timers:
General Purpose Timer (GPT)
Real-time Clock Timer (RTCT)
Watchdog Timer (WDT)
– Interrupt Controller With 5 External Inputs
– General Purpose Interface (GPI)
– Dual UART
Speed Optimized Code RAM Interface
8- or 40-bit boot-PROM (Flash) Interface
IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes
Fully Static Design
Performance: 20 MIPs/5 MFlops (double precision) at SYSCLK = 25 MHz
Core Consumption: 1.0W typ. at 20 MIPs/0.7W typ. at 10 MIPs
Operating Range: 4.5V to 5.5V (3.3V Capability) -55°C to +125°C
Total Dose Radiation Capability (Parametric and Functional): 300 KRADs (Si)
SEU Event Rate Better than 1E
-8
Error/Component/Day (Worst Case)
Latch-up Immunity Better than (LET) 100 MeV-cm
2
/mg
Quality Grades: ESA SCC, QML Q or V
Package: 256 MQFPF; Bare Die
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Rad-Hard 32-bit
SPARC
Embedded
Processor
TSC695F
Description
The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit
RISC embedded processor implementing the SPARC architecture V7 specification. It
has been developed with the support of the ESA (European Space Agency), and
offers a full development environment for embedded space applications.
The processor is manufactured using the Atmel 0.5 µm radiation tolerant (≥ 300
KRADs
(Si)
) CMOS enhanced process (RTP). It can operate at a low voltage for opti-
mized power consumption. It has been specially designed for space, as it has on-chip
concurrent transient and permanent error detection.
The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a
Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers
a high security watchdog, two timers, an interrupt controller, parallel and serial inter-
faces. Fault tolerance is supported using parity on internal/external buses and an
EDAC on the external data bus. The design is highly testable with the support of an
On-Chip Debugger (OCD), and a boundary scan through JTAG interface.
Rev. 4118F–AERO–04/02
1
Block Diagram
Figure 1.
TSC695F Block Diagram
TAP
32-bit
Integer
Unit
DMA
Arbiter
Access
Controller
Wait State
Controller
Address
Interface
EDAC
General Purpose
Interface
UART B
UART A
Interrupt
Controller
Parity
Gen./Check.
DMA Ctrl
Clock
&
Parity
Reset
Gen./Chk.
Managt
32/64-bit
Floating-Point
Unit
Parity
Gen./Chk.
Mem Ctrl
Ready/Busy
Add.+Size+ASI
Error
Managt
General Purpose
Timer
Real Time Clock
Timer
Watch
Dog
Data+Check bits
Parities
GPI bits
RxD, TxD
Interrupts
Pin Descriptions
Table 1.
Pin Descriptions
Signal
RA[31:0]
RAPAR
RASI[3:0]
RSIZE[1:0]
RASPAR
CPAR
D[31:0]
CB[6:0]
DPAR
RLDSTO
ALE
DXFER
LOCK
RD
WE
WRT
MHOLD
MDS
MEXC
PROM8
BA[1:0]
ROMCS
ROMWRT
MEMCS[9:0]
MEMWR
Type
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
O
O
I
O
O
For pin assignment, refer to package section.
Active
Description
32-bit registered address bus
Registered address bus parity
4-bit registered address space identifier
2-bit registered bus transaction size
Registered ASI and SIZE parity
Control bus parity
32-bit data bus
7-bit check-bit bus
Data bus parity
Registered atomic load-store
Address latch enable
Data transfer
Bus lock
Read access
Write enable
Advanced write
Memory bus hold
Memory data strobe
Memory exception
Select 8-bit wide PROM
Latched address used for 8-bit wide boot PROM
PROM chip select
ROM write enable
Memory chip select
Memory write strobe
Output buffer: 400 pF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHOLD+FHOLD
+BHOLD+FCCV
-
-
-
-
-
-
Output buffer: 400 pF
Output buffer: 400 pF
High
High
High
High
High
Low
High
High
High
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
2
TSC695F
4118F–AERO–04/02
TSC695F
Table 1.
Pin Descriptions (Continued)
Signal
Type
Active
Description
Output buffer: 400 pF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Used to check the execute
stage of IU
instruction pipeline
-
Input trigger
-
Input trigger
-
Input trigger
-
-
Input trigger
-
-
-
-
Input trigger
Functional mode=00
-
-
pull-up
≈
37 kΩ
pull-up
≈
37 kΩ
pull-up
≈
37 kΩ
-
-
-
O
Low
Memory output enable
OE
BUFFEN
O
Low
Data buffer enable
DDIR
O
High
Data buffer direction
DDIR
O
Low
Data buffer direction
IOSEL[3:0]
O
Low
I/O chip select
O
Low
I/O and exchange memory write strobe
IOWR
EXMCS
O
Low
Exchange memory chip select
BUSRDY
I
Low
Bus ready
BUSERR
I
Low
Bus error
DMAREQ
I
Low
DMA request
DMAGNT
O
Low
DMA grant
DMAAS
I
High
DMA address strobe
O
Low
Data ready during DMA access
DRDY
IUERR
O
Low
IU error
CPUHALT
O
Low
Processor (IU & FPU) halt and freeze
SYSERR
O
Low
System error
SYSHALT
I
Low
System halt
SYSAV
O
High
System availability
I
Low
No parity
NOPAR
INULL
O
High
Integer unit nullify cycle
INST
O
High
Instruction fetch
FLUSH
O
High
FPU instruction flush
DIA
O
High
Delay instruction annulled
RTC
O
High
Real Time Clock Counter output
RxA/RxB
I
Receive data UART "A" and "B"
TxA/TxB
O
Transmit data UART "A" and "B"
GPI[7:0]
I/O
GPI input/output
GPIINT
O
High
GPI interrupt
EXTINT[4:0]
I
External interrupt
EXTINTACK
O
High
External interrupt acknowledge
IWDE
I
High
Internal watch dog enable
EWDINT
I
High
External watch dog input interrupt
WDCLK
I
Watch dog clock
CLK2
I
Double frequency clock
SYSCLK
O
System clock
RESET
O
Low
Output reset
SYSRESET
I
Low
System input reset
TMODE[1:0]
I
Factory test mode
DEBUG
I
High
Software debug mode
TCK
I
Test (JTAG) clock
TRST
I
Low
Test (JTAG) reset
TMS
I
Test (JTAG) mode select
TDI
I
Test (JTAG) data input
TDO
O
Test (JTAG) data output
VCCI/VSSI
Main internal power
VCCO/VSSO
Output driver power
Note:
If not specified, the output buffer type is 150 pF, the input buffer type is TTL
3
4118F–AERO–04/02
System Architecture
The TSC695F is to be used as an embedded processor requiring only memory and
application specific peripherals to be added to form a complete on-board computer. All
other system support functions are provided by the core.
Figure 2.
System Architecture Based on TSC695F
DMA Unit
Ax[31:0]
Xtd PROM
Xchg Mem
Boot PROM
Master
local
memory
Glue
logic
Xtd RAM
I/O 0
to
I/O 3
DPAR
DMAGNT
DMAREQ
DMAAS
Xtd I/O
(BUFFEN, DDIR)
Xtd general
MEMCtrl
FPU
Memory
Interface
RA[31:0]
CB[6:0]
(ROMCS, EXMCS, IOSEL[3:0], MEMWR, IOWR, OE, BUSRDY,...)
RAMCtrl
(MEMCS[9:0], MEMWR, OE)
SYSCLK
ALE
RAM
Memory
DMA
A[31:0]
IU
DMA
D[31:0]
(0 ws)
Peripherals
User
Application
TSC695F
4
TSC695F
4118F–AERO–04/02
TSC695F
P
roduct
D
escription
Integer Unit
The IU is designed for highly dependable space and military applications, and includes
support for error detection. The RISC architecture makes the creation of a processor
that can execute instructions at a rate approaching one instruction per processor clock
possible.
To achieve that rate of execution, the IU employs a four-stage instruction pipeline that
permits parallel execution of multiple instructions.
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Fetch - The processor outputs the instruction address to fetch the instruction.
Decode - The instruction is placed in the instruction register and is decoded. The
processor reads the operands from the register file and computes the next
instruction address.
Execute - The processor executes the instruction and saves the results in temporary
registers. Pending traps are prioritized and internal traps are taken during this stage.
Write - If no trap is taken, the processor writes the result to the destination register.
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•
All four stages operate in parallel, working on up to four different instructions at a time. A
basic "single-cycle" instruction enters the pipeline and completes in four cycles.
By the time it reaches the write stage, three more instructions have entered and are
moving through the pipeline behind it. So, after the first four cycles, a single-cycle
instruction exits the pipeline and a single-cycle instruction enters the pipeline on every
cycle. Of course, a "single-cycle" instruction actually takes four cycles to complete, but
they are called single cycle because with this type of instruction the processor can com-
plete one instruction per cycle after the initial four-cycle delay.
Floating-point Unit
The FPU is designed to provide execution of single and double-precision floating-point
instructions concurrently with execution of integer instructions by the IU. The FPU is
compliant to the ANSI/IEEE-754 (1985) floating-point standard.
The FPU is designed for highly dependable space and military applications, and
includes support for concurrent error detection and testability.
The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and
write stages (F, D, E and W). The fetch unit captures instructions and their addresses
from the data and address busses. The decode unit contains logic to decode the float-
ing-point instruction opcodes. The execution unit handles all instruction execution. The
execution unit includes a floating-point queue (FP queue), which contains stored float-
ing-point operate (FPop) instructions under execution and their addresses. The
execution unit controls the load unit, the store unit, and the datapath unit. The FPU
depends upon the IU to access all addresses and control signals for memory access.
Floating-point loads and stores are executed in conjunction with the IU, which provides
addresses and control signals while the FPU supplies or stores the data. Instruction
fetch for integer and floating-point instructions is provided by the IU.
The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR
is a 32-bit status and control register. It keeps track of rounding modes, floating-point
trap types, queue status, condition codes, and various IEEE exception information. The
floating-point queue contains the floating-point instruction currently under execution,
along with its corresponding address.
5
4118F–AERO–04/02
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