PRELIMINARY
CY28435
Clock Generator for Intel
®
Grantsdale Chipset
Features
•
Compliant to Intel
®
CK410
• Supports Intel Prescott and Tejas CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100-MHz differential SRC clocks
• 96 MHz differential dot clock
• 48 MHz USB clocks
• 33 MHz PCI clock
• Dynamic Frequency Control
CPU
x2
SRC
x7
PCI
x9
REF
x2
DOT96
x1
USB
x2
•
Dial-A-Frequency
®
• Watchdog
• Two Independent Overclocking PLLs
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
•
56-pin SSOP and TSSOP packages
Block Diagram
Pin Configuration
Xin
Xout
14.318MHz
Crystal
PLL Reference
VDD_RE
F
RE
F
IREF
VDD_CPU
CPUT
CPUC
CPU
PLL
FS_[E:A]
Divider
VDD_CPU
ITP_EN
VDD_SRC
SRCT
SRCC
SRC
PLL
Divider
VDD_SRC
VDD_SRC
SDATA
PLL
Divider
SRCT4_SATA
SRCC4_SATA
VDD_48Mhz
FIX
PLL
Divider
DOT96T
DOT96C
VDD_48
VTTPWR_GD#/PD
USB
VDD_PCI
PCI
VDD_PCI
VSS_PCI
DF2/PCI3
*FS_E/PCI4
PCI5
VSS_PCI
VDD_PCI
**DF_EN/PCIF0
**SRESET_EN/PCIF1
PCIF2
VDD_48
USB48_0
VSS_48
DOT96T
DOT96C
*FS_B/USB48_1
**VTTPWRGD#/PD
**FS_A
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRCT4_SATA
SRCC4_SATA
VDD_SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI2/DF1
PCI1/DF0
PCI0/SRESET#
REF1/**FS_C
REF0/**FS_D
VSS_REF
XIN
XOUT
VDD_REF
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
SRCT7
SRCC7
VDD_SRC
SRCT6
SRCC6
SRCT5
SRCC5
VSS_SRC
DF_EN
DF[2:0]
VDD_PCI
Dynamic
Frequency
Watchdog
Timer
* indicates internal pull-up
** indicates internal pull-down
CY28435
PCIF
SDATA
SCLK
I2C
Logic
SRESET#
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 22
www.SpectraLinear.com
CY28435
Pin Description
Pin No.
1,7
2,6
3,55,56
4
5
8
Name
VDD_PCI
VSS_PCI
DF/PCI
FS_E/PCI4
PCI
DF_EN/PCIF0
Type
PWR
GND
3.3V power supply for outputs.
Ground for outputs.
Description
I/O, SE
3.3V LVTTL input to enable Dynamic Frequency input/33-MHz clock output.
I/O,PU,
3.3V-tolerant input for CPU frequency selection/33-MHz clock.
SE
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
O, SE
33-MHz clock.
I/O, SE,
3.3V LVTTL input to enable Dynamic Frequency input/33-MHz clock output.
PD (sampled on the VTT_PWRGD# assertion).
1 = Enable, 0 = Disable
9
10
17
SRESET_EN/PCIF I/O, SE,
3.3V LVTTL input to enable Watchdog/33-MHz clocks.
1
PD 1 = Enable, 0 = Disable
PCIF2
VTT_PWRGD#/PD
O, SE
33-MHz clocks.
I, PD
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C,FS_D and FS_E inputs.
After VTT_PWRGD# (active LOW) assertion,
this pin becomes a real-time input for asserting power down (active HIGH).
3.3V power supply for outputs.
48-MHz clock output.
3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
11
12
18
13
14,15
16
VDD_48
USB48_0
FS_A
VSS_48
DOT96T, DOT96C
FS_B/USB48_1
PWR
O
I, PD
GND
O, DIF
Fixed 96 MHz clock output.
I/O, PU,
3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
SE
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
O, DIF
Differential serial reference clocks.
Outputs have overclocking capability.
19,20,22,23, SRCT/C
24,25,30,31,
32,33,36, 35
21,28,34
26,27
29
37
38
39
42
41,40,44,43
45
46
47
48
49
50
51
52
VDD_SRC
SRC4_SATAT,
SRC4_SATAC
VSS_SRC
VDDA
VSSA
IREF
VDD_CPU
CPUT/C
VSS_CPU
SCLK
SDATA
VDD_REF
XOUT
XIN
VSS_REF
FS_D/REF0
PWR
3.3V power supply for outputs.
O, DIF
Differential serial reference clock.
Recommended output for SATA.
GND
PWR
GND
I
PWR
GND
I
I/O
PWR
I
GND
Ground for outputs.
3.3V power supply for PLL.
Ground for PLL.
A precision resistor is attached to this pin,
which is connected to the internal
current reference.
3.3V power supply for outputs.
Ground for outputs.
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
3.3V power supply for outputs.
14.318 MHz crystal input.
Ground for outputs.
O, DIF
Differential CPU clock outputs.
O, SE
14.318 MHz crystal output.
I/O, SE,
3.3V-tolerant input for CPU frequency selection/Reference clock.
PD
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Rev 1.0, November 20, 2006
Page 2 of 22
CY28435
Pin Description
(continued)
Pin No.
53
Name
FS_C/REF1
Type
I/O,
PD
Description
3.3V-tolerant input for CPU frequency selection/Reference clock.
Selects test mode if pulled to V
IHFS_C
when VTT_PWRGD# is asserted LOW.
Refer to DC Electrical Specifications table for
V
ILFS_C
,V
IMFS_C
,V
IHFS_C
specifica-
tions.
54
SRESET#/PCI0
O, PU
3.3V LVTTL output for Watchdog reset/33-MHz clock output.
When configured as SRESET# output this output becomes open drain type with a
high (>100 kΩ) internal pull-up resistor.
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Frequency Select Pins (FS_[A:E])
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C, FS_D, and
FS_E inputs prior to VTT_PWRGD# assertion (as seen by the
clock synthesizer). Upon VTT_PWRGD# being sampled LOW
by the clock chip (indicating processor VTT voltage is stable),
the clock chip samples the FS_A, FS_B, FS_C, FS_D, and
FS_E input values. For all logic levels of FS_A, FS_B, FS_C,
FS_D, and FS_E, VTT_PWRGD# employs a one-shot
functionality in that once a valid LOW on VTT_PWRGD# has
been sampled, all further VTT_PWRGD#, FS_A, FS_B, FS_C,
FS_D, and FS_E transitions will be ignored, except in test
mode.
FS_C is a three-level input. When sampled at a voltage greater
than 2.1V by VTTPWRGD#, the device will enter test mode as
selected by the voltage level on the FS_B input.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
Input Conditions
FS_D
FS_C
FS_B
FS_A
Output Frequency
CPU
SRC
SRC M
CPU PLL CPU M CPU N CPU N SRC PLL
SRC N
SRC N
divider (not DEFAULT allowable
Gear
divider DEFA
ULT allowable
Gear
Constants
range for Constants changeable
range for
by user)
DAF
DAF
(G)
FSEL_3
FSEL_2
FSEL_1
FSEL_0
(MHz)
(MHz)
0
0
0
0
0
0
0
1
1
1
1
1
1
1
X
X
1
0
0
0
0
1
1
1
0
0
0
0
1
1
HIGH
HIGH
0
0
1
1
0
0
1
0
0
1
1
0
0
1
LOW
HIGH
1
1
1
0
0
0
0
1
1
1
0
0
0
0
X
X
100
133.3333333
166.6666667
200
266.6666667
333.3333333
400
100.952381
133.968254
167
200.952381
266.6666667
334
400.6451613
Tristate
REF/N
100
100
100
100
100
100
100
100
100
100
100
100
100
100
Tristate
REF/N
30
40
60
60
80
120
120
30
40
60
60
80
120
120
Tristate
REF/N
60
60
63
60
60
63
60
63
63
60
63
60
60
62
Tristate
REF/N
200
200
175
200
200
175
200
212
211
167
211
200
167
207
Tristate
REF/N
200 - 250
200 - 250
175 - 262
200 - 250
200 - 250
175 - 262
200 - 250
212 - 262
211 - 262
167 - 250
211 - 262
200 - 250
167 - 250
207 - 258
Tristate
REF/N
30
30
30
30
30
30
30
30
30
30
30
30
30
30
60
60
60
60
60
60
60
60
60
60
60
60
60
60
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 167 - 266
200 167 - 266
Figure 1. CPU and SRC Frequency Select Tables
Rev 1.0, November 20, 2006
Page 3 of 22
CY28435
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
Rev 1.0, November 20, 2006
Page 4 of 22
CY28435
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
SRC[T/C]7
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4_SATA
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
RESERVED
Description
SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4_SATA Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
RESERVED, Set = 1
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
0
1
1
0
Name
PCIF0
DOT_96T/C
USB48_0
REF0
RESERVED
CPU[T/C]1
CPU[T/C]0
CPU
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB48_0 MHz Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
RESERVED, Set = 0
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Description
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
@Pup
1
1
1
1
1
1
1
Name
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
PCIF2
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
Description
Rev 1.0, November 20, 2006
Page 5 of 22
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