Features
•
Also known as SMCS116SpW
•
Single
Bidirectional SpaceWire link allowing
– Full duplex communication
– Transmit rate from 1.25 up to 200 Mbit/s in each direction
– Supports Serial Transfer Universal Protocol (STUP)
Derived from the T7906 Single Point to Point IEEE 1355 High Speed Controller
– Known anomalies of the T7906 chip corrected
Host interface
– Gives read/write accesses to the AT7912F configuration registers
– Gives read/write accesses to the SpaceWire channel
ADC/ DAC interface
– Allows direct connection of an ADC with a width of up to 16 bits
– Allows direct connection of a DAC with up to 16 data lines and the required control
signals
FIFO interface
RAM interface
– 16-bit data bus and 16-bit address bus
– Four chip selects to address 4 different memory partitions
Two independent UART interfaces
24 Bidirectional General Purpose I/Os
Two 32-Bit Timers / Event Counters
SpaceWire Link Performance
– At 3.3V : 100Mbit/s full duplex communication
– At 5V : 200Mbit/s full duplex communication
Operating range
– Voltages
• 3V to 3.6V
• 4.5V to 5.5V
– Temperature
• - 55° to +125°
C
C
Maximum Power consumption
– At 3.6V with a 5MHz clock: 150mW
– At 5.5V with a 5MHz clock: 700mW
Radiation Performance
– Total dose tested successfully up to 50 Krad (Si)
– No single event latchup below a LET of 80 MeV/mg/cm2
ESD better than 2000V
Quality Grades
– QML-Q or V with SMD
Package: 100pins MQFPF
Mass: 3grams
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Single
SpaceWire link
High Speed
Controller
AT7912F
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7829A–AERO–10/08
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1. Description
The AT7912F provides an interface between a SpaceWire link according to the Space-
Wire Standard ECSS-E-50-12A and several different interfaces.
The AT7912F was designed by EADS Astrium in Germany under the name
'SMCS116SpW" for "Scalable Multi-channel Communication Subsystem for Space-
Wire". It is manufactured using the SEU hardened cell library from Atmel MG2RT
CMOS 0.5µm radiation tolerant sea of gates technology.
For any technical question relative to the functionality of the AT7912F please contact
Atmel technical support at
assp-applab.hotline@nto.atmel.com.
This document should be read in conjunction with
EADS Astrium 'SMCS116SpW User
Manual'.
This user manual is available at
www.atmel.com.
A block diagram of the AT7912F is given in figure 1.
Figure 1.
AT7912F Block Diagram
The AT7912F provides one SpaceWire serial communication link with up to 200 Mbit/s
data transmit rate. It features a link disconnect detection and parity check at character
2
7829A–AERO–10/08
level as well as an additional checksum generation/check at packet level. The AT7912F
supports both the standard SpaceWire link protocol (transparent mode) and the STUP
(Serial Transfer Universal Protocol) for efficient packet oriented data transfer.
In addition to the serial SpaceWire link, the AT7912F provides several different
interfaces:
• Host interface
• ADC interface
• DAC interface
• RAM interface
• FIFO interface
• General purpose I/O
• UART interfaces
• Timers / Event Counters
• JTAG (IEEE 1149.1)
2. Pin Configuration
Table 2-1.
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Pin assignment
Name
Pin
Number
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
IOB9
VCC
GND
IOB10
IOB11
IOB12
IOB13
IOB14
IOB15
IOB16
IOB17
IOB18
IOB19
IOB20
IOB21
IOB22
IOB23
IOB24
IOB25
IOB26
IOB27
DATA0
DATA1
DATA2
DATA3
Pin
Number
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
DATA4
DATA5
DATA6
DATA7
DATA8
VCC
GND
DATA9
DATA10
DATA11
VCC
GND
DATA12
DATA13
DATA14
DATA15
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
TMR1_CLK
Pin
Number
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
TMR2_CLK
RxD1
TMR1_EXP
TMR2_EXP
TxD1
HDATA0
HDATA1
HDATA2
HDATA3
HDATA4
HDATA5
HDATA6
VCC
GND
HDATA7
HDATNADR*
HSEL*
HWRNRD
HINTR*
RESET*
CLK
VCC_3VOLT
GND
GND
VCC
PLLOUT
GND
VCC
VCC
LDO
LSO
LDI
LSI
GND
TCK
TMS
TDI
TRST*
TDO
GND
VCC
IOB0
IOB1
IOB2
IOB3
IOB4
IOB5
IOB6
IOB7
IOB8
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3. Pin Description
Table 3-1.
Pin description
5V
±
0.5V
max. output
current [mA]
3.3V
±
0.3V
max. output
current [mA]
Signal Name
(1)(3)
HSEL*
Type
(2)(4)
I
Function
When low, the external host selects the AT7912F host
interface
Host interface write/read signal
load [pF]
HWRnRD
I
if HWRnRD is high during HSEL* low, the host writes data to
the address register or to the AT7912F registers.
if HWRnRD is low during HSEL* low, the host reads data
from the address register or the AT7912F registers.
Host interface data/address signal
HDATnADR
I
if HDATnADR is high during read, the host reads/writes data
from/to the internal AT7912F (data) registers.
if HDATnADR is low during read, the host
reads/writes address from/to the address register.
AT7912F data bus.
HDATA(7:0)
I/O/Z
HDATA(7:0) can be used as GPIO(2), if the Host interface is
disabled
Host interrupt request line
Timer1 clock (max. 12.5 MHz)
Timer1 expired. Asserted for one cycle if the value of
counter1 is equal to the content of register TPERIOD1(3:0).
Timer2 clock (max. 12.5 MHz)
Timer2 expired. Asserted for one cycle if the value of
counter2 is equal to the content of register TPERIOD2(3:0).
Receive data to UART1
Transmit data from UART1
Link Data Input
Link Strobe Input
Link Data Output
Link Strobe Output
Common AT7912F data bus
General purpose input/output lines
3
1.5
50
HINTR*
TMR1_CLK
TMR1_EXP
TMR2_CLK
TMR2_EXP
RxD1
TxD1
LDI
LSI
LDO
LSO
DATA(15:0)
GPIO(7:0)
IOB(21:0)
IOB(24:22)
IOB27
IOB(26:25)
O
I
O
I
O
I
O
I
I
O
O
I/O/Z
I/O
I/O
I/O
I
3
1.5
50
3
1.5
50
3
1.5
50
3
1.5
50
12
12
3
3
6
6
6
1.5
1.5
3
1.5
25
25
25
25
25
25
Control bus.
The AT7912F controls the connected interface via these
lines.
3
TRST*
I
Test Reset. Resets the test state machine
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Table 3-1.
Pin description (Continued)
5V
±
0.5V
max. output
current [mA]
3.3V
±
0.3V
max. output
current [mA]
Signal Name
(1)(3)
TCK
Type
(2)(4)
I
Function
Test Clock. Provides an asynchronous clock for JTAG
boundary scan
Test Mode Select.
load [pF]
TMS
I
Used to control the test state machine. This input should be
left unconnected or tied to ground during normal operation
Test Data Input.
Provides serial data for the boundary scan logic
Test Data Output.
Serial scan output of the boundary scan path
AT7912F Reset.
3
1.5
50
TDI
I
TDO
O/Z
RESET*
I
Sets the AT7912F to a known state. This input must be
asserted (low) at power-up. The minimum width of RESET
low is 2 cycles when CLK is running
External clock input to AT7912F (max. 5 MHz)
Output of internal PLL.
Used to connect a network of external RC filter devices.
PLL Control signal
CLK
PLLOUT
I
O
VCC_3VOLT
I
Configure PLL for 3.3V or 5V operation
VCC = 5 Volt: connect this signal with GND
VCC = 3.3 Volt: connect this signal with VCC
VCC
GND
Power Supply
Ground
Notes:
1. Groups of pins represent busses where the highest number is the MSB.
2. O = Output; I = Input; Z = High Impedance
3. (*) = active low signal
4. O/Z = if using a configuration with two AT7912Fs these signals can directly be con-
nected together (WIROR)
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7829A–AERO–10/08
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