12338\CYW2338
PRELIMINARY
CYW2338
Dual Serial Input PLL with 2.5- and 1.1-GHz Prescalers
Features
• Operating voltage 2.7V to 5.5V
• Operating frequency to 2.5 GHz on PLL1 and 1.1 GHz
on PLL2 with prescaler ratios of 64/65 and 128/129
• Lock detect feature
• Power-down mode I
CC
< 1 µA typical at 3.0V
• Serial data input accepts data clock rates as low as
1 kHz
• Low power/voltage operation with low current standby
mode
• On-chip reference oscillator
• Available in a 20-pin TSSOP (Thin Shrink Small Outline
Package)
• Available in a 24-pin CSP (Chip Scale Package)
• Available in a 20-pin MLF
(Mirco Lead Frame Package)
Applications
The Cypress CYW2338 is a dual serial input PLL frequency
synthesizer designed for high performance dual conversion
TV, VCR, and Set-top tuner sections, as well as downstream
receivers for cable modems. The CYW2338 is also well suited
for high-volume, low-cost wireless communications applica-
tions. One 2.5-GHz and 1.1-GHz prescaler, each with pulse
swallow capability are included. The device operates from
2.7V and dissipates only 27 mW.
Dual PLL Block Diagram
F
IN
1 (5)
F
IN
1# (6)
Prescaler
64/65 or
128/129
GND (4)
GND (7)
V
CC
1 (1)
V
CC
2 (20)
V
P
1 (2)
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
fp1
Phase
Detector
Charge
Pump
D
O
PLL1 (3)
19-Bit
Latch
OSC_IN (8)
OSC_OUT (9)
Latch
Selector
LE (13)
DATA (12)
CLOCK (11)
Pwr-dwn
PLL1
fr1
fr fp
Monitor
Output
Selector
15-Bit
Reference Counter
20-Bit Latch
20-Bit Latch
15-Bit
Reference Counter
19-Bit
Latch
Pwr-dwn
PLL2
F
O
/LD (10)
fr2
Cntrl 22-Bit
Shift
Reg.
Power
Control
F
IN
2 (16)
F
IN
2# (15)
Prescaler
64/65 or
128/129
Binary 4-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
Phase
Detector
fp2
Charge
Pump
D
O
PLL2 (18)
GND (14)
Vcc1
Vcc2
GND (17)
V
P
2 (19)
Pin Configuration
V
CC
1
V
P
1
D
O
PLL1
GND
F
IN
1
F
IN
1#
GND
OSC_IN
OSC_OUT
F
O
/LD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
2
V
P
2
D
O
PLL2
GND
F
IN
2
F
IN
2#
GND
LE
DATA
CLOCK
NC
Vp1
DoPLL1
GND
Fin1
Fin1#
GND
OSC_IN
NC
1
2
3
4
5
6
7
8
Vp2
Vp1
20
19
18
DoPLL2
20
19
18
17
Vp2
24
23
22
21
NC
GND
Fin2
Fin2#
GND
LE
DATA
NC
DoPLL1
GND
Fin1
Fin1#
GND
16
DoPLL2
Vcc1
Vcc2
1
2
3
4
5
10
6
15
14
GND
Fin2
Fin2#
GND
LE
(Top View)
17
16
15
14
(Top View)
13
12
11
10
11
12
7
8
9
13
OSC_OUT
GND
Fo/LD
CLOCK
Fo/LD
9
OSC_OUT
GND
TSSOP
CSP
OSC_IN
MLF
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
February 6, 2001, rev. **
CLOCK
DATA
PRELIMINARY
Pin Definitions
Pin Name
V
CC
1
Pin
No.
(TSSOP)
1
Pin
No.
(CSP)
24
Pin
No.
(MLF)
19
Pin
Type
P
Pin Description
CYW2338
Power Supply Connection for PLL1 and PLL2:
When pow-
er is removed from both the V
CC
1 and V
CC
2 pins, all latched
data is lost.
PLL1 Charge Pump Rail Voltage:
This voltage accommo-
dates VCO circuits with tuning voltages higher than the V
CC
of PLL1.
PLL1 Charge Pump Output:
The phase detector gain is
I
P
/2π. Sense polarity can be reversed by setting the FC bit in
software (via the Shift Register).
Input to PLL1 Prescaler:
Maximum frequency 2.5 GHz.
Complementary Input to PLL1 Prescaler:
A bypass capac-
itor should be placed as close as possible to this pin and must
be connected directly to the ground plane.
Oscillator Input:
This input has a V
CC
/2 threshold and CMOS
logic level sensitivity.
Oscillator Output
Lock Detect Pin of PLL1 Section:
This output is HIGH when
the loop is locked. It is multiplexed to the output of the pro-
grammable counters or reference dividers in the test program
mode. (Refer to
Table 3
for configuration.)
Data Clock Input:
One bit of data is loaded into the Shift
Register on the rising edge of this signal.
Serial Data Input
Load Enable:
On the rising edge of this signal, the data stored
in the Shift Register is latched into the reference counter and
configuration controls, PLL1 or PLL2 depending on the state
of the control bits.
Complementary Input to PLL2 Prescaler:
A bypass capac-
itor should be placed as close as possible to this pin and must
be connected directly to the ground plane.
Input to PLL2 Prescaler:
Maximum frequency 1.1 GHz.
PLL2 Charge Pump Output:
The phase detector gain is
I
P
/2π. Sense polarity can be reversed by setting the FC bit in
software (via the Shift Register).
PLL2 Charge Pump Rail Voltage:
This voltage accommo-
dates VCO circuits with tuning voltages higher than the V
CC
of PLL2.
Power Supply Connections for PLL1 and PLL2:
When
power is removed from both the V
CC
1 and V
CC
2 pins, all
latched data is lost.
Analog and Digital Ground Connections:
This pin must be
grounded.
No Connect.
V
P
1
2
2
20
P
D
O
PLL1
3
3
1
O
F
IN
1
F
IN
1#
5
6
5
6
3
4
I
I
OSC_IN
OSC_OUT
F
O
/LD
8
9
10
8
10
11
6
7
8
I
O
O
CLOCK
DATA
LE
11
12
13
12
14
15
9
10
11
I
I
I
F
IN
2#
15
17
13
I
F
IN
2
D
O
PLL2
16
18
18
20
14
16
I
O
V
P
2
19
22
17
P
V
CC
2
20
23
18
P
GND
N/C
4, 7, 14,
17
N/A
4, 7, 16,
19
1, 9, 13,
21
2, 5, 12,
15
N/A
G
N/C
2
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
Parameter
V
CC
or V
P
V
OUT
I
OUT
T
L
T
STG
Output Voltage
Output Current
Lead Temperature
Storage Temperature
Description
Power Supply Voltage
CYW2338
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Rating
–0.5 to +6.5
–0.5 to V
CC
+0.5
±15
+260
–55 to +150
Unit
V
V
mA
°C
°C
Handling Precautions
Devices should be transported and stored in antistatic con-
tainers.
These devices are static sensitive. Ensure that equipment and
personnel contacting the devices are properly grounded.
Cover workbenches with grounded conductive mats.
Always turn off power before adding or removing devices from
system.
Protect leads with a conductive sheet when handling or trans-
porting PC boards with devices.
If devices are removed from the moisture protective bags for
more than 36 hours, they should be baked at 85°C in a mois-
ture free environment for 24 hours prior to assembly in less
than 24 hours.
Recommended Operating Conditions
Parameter
V
CC1
,
V
CC2
V
P
T
A
Description
Power Supply Voltage
Charge Pump Voltage
Operating Temperature
Ambient air at 0 CFM flow
Test Condition
Rating
2.7 to 5.5
V
CC
to +5.5
–40 to +85
Unit
V
V
°C
3
PRELIMINARY
Electrical Characteristics:
V
CC
= V
P
= 2.7V to 5.5V, T
A
= –40°C to +85°C, Unless otherwise specified
Parameter
I
CC
I
PD
F
IN
1
F
IN
2
F
OSC
Fφ
PF
IN
1
PF
IN
2
V
OSC
I
IH
, I
IL
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
ID
OH(SO)
ID
OL(SO)
ID
OH(SI)
ID
OL(SI)
∆ID
O
Oscillator Input Sensitivity
High/Low Level Input
Current
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High level Output Voltage
Low Level Output Voltage
ID
O
High, Source Current
ID
O
Low, Source Current
ID
O
High, Sink Current
ID
O
Low, Sink Current
ID
O
Charge Pump Sink and
Source Mismatch
Charge Pump Current
Variation vs. Temperature
Charge Pump High-Imped-
ance Leakage Current
V
CC
= V
P
= 3.0V,
[IID
O(SI)
I – IID
O(SO)
I]/
[1/2*{IID
O(SI)
]I+IID
O(SO)
I}]*100%
–40°C<T<85°C V
DO
= V
P
/2
[1]
V
CC
= V
P
= 3.0V,
V
CC
= 3.0V, I
OH
= -1 mA
V
CC
= 3.0V, I
OL
= 1 mA
V
CC
= V
P
= 3.0V,
D
O
= V
P
/2
F
O
/LD
D
O
PLL1
D
O
PLL2
V
CC
= 3.0V
DATA,
CLOCK,
LE
Oscillator Input Frequency
Phase Detector Frequency
Input Sensitivity
V
CC
= 2.7V
V
CC
= 5.5V
V
CC
= 2.7V to 5.5V
V
CC
= 3.0V
F
IN
2
OSC_IN
F
IN
1
–15
–10
–10
0.5
-100
V
CC
* 0.8
Description
Power Supply Current
PLL1 + PLL2
Power-down Current
Operating Frequency
Test Condition
V
CC
1 = V
CC
2 = 3.0V
Power-down, V
CC
= 3.0V
PLL1
PLL2
No load on OSC_OUT
With OSC_OUT loaded
Pin
V
CC
1,
V
CC
2
V
CC
1,
V
CC
2
F
IN
1
F
IN
2
OSC_IN
100
45
5
5
Min.
Typ.
10
1
CYW2338
Max.
Unit
mA
25
2500
1100
45
25
10
4
4
4
100
µA
MHz
MHz
MHz
MHz
MHz
dBm
dBm
dBm
V
P–P
µA
V
V
CC
* 0.2
–10
–10
V
CC
* 0.8
V
CC
* 0.2
–3.8
–1
3.8
1
3
15
0.5
0.5
10
10
V
µA
µA
V
V
mA
mA
mA
mA
%
ID
O
vs T
I
OFF
5
±2.5
%
nA
Note:
1. ID
O
vs T; Charge pump current variation vs. temperature.
[IID
O(SI)@T
I - IID
O(SI)@25° C
I]/IID
O(SI)@25°C
I * 100% and
[IID
O(SO)@T
I - IID
O(SO)@25°C
I]/IID
O(SO)@25°C
I *100%.
4
PRELIMINARY
Timing Waveforms
Key:
CYW2338
FC Bit HIGH
FC Bit LOW
(Refer to
Table 2
for meaning of FC bit.)
Increasing Frequency
VCO Characteristics
Phase Comparator Sense
Increasing
Voltage
Phase Detector Output Waveform
F
R
F
P
tw
tw
LD
D
O
Charge Pump Output Current Waveform
F
R
F
P
tw
tw
D
o
ID
O
Hi-Impedance State
5
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