MK3720
27 MH
Z AND
54 MH
Z
3.3 V
OLT
VCXO
Description
The MK3720D and MK3720B are drop-in replacements
for the MK3720S and MK3720A devices. Compared to
these earlier devices the MK3720D and MK3720B offer
a wider operating frequency range and improved power
supply noise rejection.
The MK3720 is a low cost, low jitter, high performance
3.3 Volt VCXO designed to replace expensive 13.5, 27,
or 54 MHz VCXOs. The patented on-chip Voltage
Controlled Crystal Oscillator accepts a 0 to 3.3 V input
voltage to cause the output clocks to vary by ±100
ppm. Using ICS’ patented VCXO and analog/digital
Phase-Locked Loop (PLL) techniques, the device uses
an inexpensive external pullable crystal input to
produce output clocks of 13.5 MHz, 27 MHz, and 54
MHz.
The MK3720D exhibits a moderate VCXO gain of
120ppm/V typical, when used with a high quality
external pullable quartz crystal. The MK3720B offers a
higher VCXO gain of 150ppm/V, similar to the earlier
MK3720A. The higher intrinsic VCXO gain of the
MK3720B may help compensate for the reduced
pullability of a low quality crystal used in some
applications. However, higher VCXO gain may also
increase clock output phase noise.
The frequency of the on-chip VCXO is adjusted by an
external control voltage input into pin VIN. Because
VIN is a high impedance input, it can be driven directly
from an PWM RC integrator circuit.
Features
•
MK3720D and MK3720B are drop-in upgrades to the
earlier MK3720S and MK3720A devices
•
•
•
•
•
Packaged in 8 pin SOIC
Operating voltage of 3.3 V (±5%)
Output clocks of 54, 27, and 13.5 MHz
Uses an inexpensive 13.500 MHz external crystal
On-chip VCXO (patented) with pull range of 200ppm
(minimum)
•
VCXO tuning voltage of 0 to 3.3V
•
12mA output drive capability at TTL levels
•
Advanced, low power, sub-micron CMOS process
MK3720D is Recommended for New Designs
Block Diagram
VDD
V IN
54 M Hz
1 3 .5 M H z
P u lla b le
C ry s tal
X1
V o lta g e
C o n tro lle d
C ry sta l
O scilla to r
P L L/C lo c k
S yn th e sis
C ircu itry
27 M Hz
1 3 .5 M H z
X2
GND
MDS 3720 F
In tegr ated C ir cu it S yst ems
q
1
5 25 Ra ce Str eet, San Jose, C A 95 126
q
Revision 102301
tel ( 408) 2 95-9 800
q
www. i c s t. c om
MK3720
27 MH
Z AND
54 MH
Z
3.3 V
OLT
VCXO
Pin Assignment
X1
VDD
VIN
GND
1
2
3
4
MK3720B
MK3720D
8 Pin (150 mil) SOIC
8
7
6
5
X2
27M
13.5M
54M
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
XI
VDD
VIN
GND
54M
13.5
27
X2
Pin
Type
Input
Power
Input
Power
Pin Description
Crystal connection. Connect to the external pullable crystal.
Connect to +3.3 V (0.01uf decoupling capacitor recommended).
Voltage input to VCXO. Zero to 3.3 V analog input which controls the
oscillation frequency of the VCXO.
Connect to ground.
Output 54 MHz VCXO clock output.
Output 13.5 MHz VCXO clock output.
Output 27 MHz VCXO clock output.
Input
Crystal connection. Connect to the external pullable crystal.
MDS 3720 F
Int egrat ed C ircuit Syste ms
q
2
525 R ace S tr eet, San Jose, CA 95126
q
Revision 102301
t el (40 8) 295 -9800
q
w ww. ic s t .c o m
MK3720
27 MH
Z AND
54 MH
Z
3.3 V
OLT
VCXO
External Component Selection
The MK3720 requires a minimum number of external
components for proper operation.
should be no signal traces underneath or close to the
crystal.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors
is determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK3720 to 3.3V. Connect pin 3
of the MK3720 to the second power supply. Adjust the
voltage on pin 3 to 0V. Measure and record the
frequency of the CLK output.
2. Adjust the voltage on pin 3 to 3.3V. Measure and
record the frequency of the same output.
To calculate the centering error:
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD (pin 2) and GND (pin 4), as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output (CLK,
pin 5) and the load is over 1 inch, series termination
should be used. To series terminate a 50Ω trace (a
commonly used trace impedance) place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Quartz Crystal
The MK3720 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section shown must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The MK3720 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the MK3720 is designed to have zero frequency
error when the total of on-chip + stray capacitance is
14pF.
Recommended Crystal Parameters:
See application note MAN05 for crystal information.
MAN05 is available on the internet at
www.icst.com/pdf/man05.pdf.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the MK3720. There should be no via’s between
the crystal pins and the X1 and X2 device pins. There
6
(
f
3.0V
–
f
t arg et
)
+
(
f
0V
–
f
t arg et
)
Error = 10 x ------------------------------------------------------------------------------
–
error
xtal
f
t arg et
Where:
f
target
= nominal crystal frequency
error
xtal
=actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±25 ppm, no
adjustment is needed. If the centering error is more
than 25ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS MicroClock for details.) If the
centering error is more than 25ppm positive, add
MDS 3720 F
Int egrat ed C ircuit Syste ms
q
3
525 R ace S tr eet, San Jose, CA 95126
q
Revision 102301
t el (40 8) 295 -9800
q
w ww. ic s t .c o m
MK3720
27 MH
Z AND
54 MH
Z
3.3 V
OLT
VCXO
identical fixed centering capacitors from each crystal
pin to ground. The value for each of these caps (in pF)
is given by:
External Capacitor =
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied
by your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (typically less than ±25ppm).
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3720. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5V to VDD+0.5V
0 to +70°C
-65 to +150°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Reference crystal parameters
Min.
0
+3.15
Typ.
–
Max.
+70
+3.45
Units
°C
V
Refer to page 3
MDS 3720 F
Int egrat ed C ircuit Syste ms
q
4
525 R ace S tr eet, San Jose, CA 95126
q
Revision 102301
t el (40 8) 295 -9800
q
w ww. ic s t .c o m
MK3720
27 MH
Z AND
54 MH
Z
3.3 V
OLT
VCXO
DC Electrical Characteristics
VDD=3.3V ±5%
, Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Operating Supply Current
Short Circuit Current
VIN, VCXO Control Voltage
Symbol
VDD
V
OH
V
OL
V
OH
IDD
I
OS
V
IA
Conditions
I
OH
= -12 mA
I
OL
= 12 mA
I
OH
= -4 mA
No load
Min.
3.15
2.4
Typ.
Max.
3.45
0.4
Units
V
V
V
V
VDD-0.4
13
±50
0
3.3
mA
mA
V
AC Electrical Characteristics
VDD = 3.3V ±5%
, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Crystal Pullability
VCXO Gain
MK3720D, Note 3
MK3720B, Note 3
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Maximum Output Jitter,
short term
t
OR
t
OF
t
D
t
J
VIN = VDD/2 + 1V, Note 1
VIN = VDD/2 + 1V, Note 1
0.8 to 2.0V, C
L
=15pF
2.0 to 0.8V, C
L
=15pF
Measured at 1.4V, C
L
=15pF
C
L
=15pF, 13.5M CLK
C
L
=15pF, 27M and 54M CLK
Note 2: Original MK3720S and MK3720A provided + 100 ppm crystal pullability.
Note 3: Original MK3720S and MK3720A provided 100 and 170 ppm/V respectively.
45
50
80
150
120
150
1.5
1.5
55
ppm/V
ppm/V
ns
ns
%
ps
ps
Symbol
F
P
Conditions
0V< VIN < 3.3V, Note 1
Min.
+ 115
Typ.
Max. Units
ppm
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
MDS 3720 F
Int egrat ed C ircuit Syste ms
q
5
525 R ace S tr eet, San Jose, CA 95126
q
Revision 102301
t el (40 8) 295 -9800
q
w ww. ic s t .c o m
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
