HV57009
64-Channel Serial To Parallel Converter
With P-Channel Open Drain Controllable Output Current
Ordering Information
Package Options
Device
80-Lead Quad
Ceramic Gullwing
80 Lead Quad
Plastic Gullwing
Die
80 Lead Quad
Ceramic Gullwing
(MIL-Std-833 Processed*)
RBHV57009DG
HV57009
HV57009DG
HV57009PG
HV57009X
* For Hi-Rel process flows, refer to page 5-3 of the Databook.
Features
❏
Processed with HVCMOS
®
technology
❏
5V CMOS Logic
❏
Output voltage up to -85V
❏
Output current source control
❏
16MHz equivalent data rate
❏
Latched data outputs
❏
Forward and reverse shifting options (DIR pin)
❏
Diode to V
DD
allows efficient power recovery
❏
Hi-Rel processing available
General Description
The HV570 is a low-voltage serial to high-voltage parallel con-
verter with P-channel open drain outputs. This device has been
designed for use as a driver for plasma panels.
The device has two parallel 32-bit shift registers, permitting data
rate twice the speed of one (they are clocked together). There
are also 64 latches and control logic to perform the blanking of
the outputs. HV
OUT
1 is connected to the first stage of the first shift
register through the blanking logic. Data is shifted through the
shift registers on the logic low to high transition of the clock. The
DIR pin causes CCW shifting when connected to V
SS
, and CW
shifting when connected to V
DD
. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register (HV
OUT
64). Operation of the shift
register is not affected by the LE (latch enable), or the BL
(blanking) inputs. Transfer of data from the shift registers to
latches occurs when the LE input is high. The data in the latches
is stored when LE is low.
The HV570 has 64 channels of output constant current sourcing
capability. They are adjustable from 0.1 to 2.0mA through one
external resistor or a current source.
Absolute Maximum Ratings
Supply voltage, V
DD1
Output Voltage, V
NN1
Logic input levels
1
Ground Current
2
Continuous total power dissipation
3
Plastic
Ceramic
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
-0.5V to +7.5V
V
DD
+ 0.5V to -95V
-0.3V to V
DD
+0.3V
1.5A
1200mW
1900mW
Plastic
-40°C to +85°C
Ceramic -55°C to +125°C
-65°C to +150°C
260°C
Notes:
1. All voltages are referenced to V
SS
.
2. Limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20mW/°C for plastic and at 19mW/°C for ceramic.
01/14/03
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1
HV57009
Electrical Characteristics
DC Characteristics
(All voltages are referenced to V
SS
, V
SS
= 0, TA = 25°C)
Symbol
I
DD
I
NN
I
DDQ
V
OH
V
OL
I
IH
I
IL
I
CS
Parameter
V
DD
supply current
High voltage supply current
Quiescent V
DD
supply current
High-level output
Data out
HV
OUT
Low-level output
High-level logic input current
Low-level logic input current
HV output source current
-0.1
∆I
CS
HV output source current for I
REF
= 2.0mA
10
Data out
V
DD
-0.5
+1
V
DD
+0.5
1
-1
-2
Min
Max
15
-10
100
Units
mA
µA
µA
V
V
V
µA
µA
mA
mA
%
Conditions
V
DD
= V
DD
, max
f
CLK
= 8MHz
Outputs off, HV
OUT
= -85V
(total of all outputs)
All inputs = V
DD
, except
+IN = V
SS
= GND
I
O
= -100µA
I
O
= -2mA
I
O
= 100µA
V
IH
= V
DD
V
IL
= 0V
V
REF
= 2V, R
EXT
= 1K,
see Figures 8a and 8b
V
REF
= 0.1V, R
EXT
= 1K,
see Figure 8a and 8b
V
REF
= 2V, R
EXT
= 1K
Notes
1: Current going out of the chip is considered negative.
AC Characteristics
(Logic signal inputs and Data inputs have t
r
, t
f
≤
5ns [10% and 90% points] for measurements)
Symbol
f
CLK
f
CLK
t
WL
, t
WH
t
SU
t
H
t
ON
, t
OFF
t
DHL
t
DLH
t
DLE
t
WLE
t
SLE
t
r
, t
f
Parameter
Clock frequency
Clock frequency
Clock width high or low
Data set-up time before clock rises
Data hold time after clock rises
Time for latch enable to HV
OUT
Delay time clock to data high to low
Delay time clock to data low to high
Delay time clock to LE low to high
Width of LE pulse
LE set-up time before clock rises
Maximum allowable clock rise and fall time
(10% and 90% points)
45
25
0
100
Min
DC
DC
62
20
15
500
150
150
Max
8
4.5
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 15pF
C
L
= 15pF
C
L
= 15pF
Conditions
Per register
When cascading devices
2
FPGA/CPLD
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